rphlx

17 ms·

91.
by rphlx 9y ago
There are some hobbyists using the 28nm Xilinx Zynq, a hardened circa-2009-cell-phone dual-core ARM with on-die FPGA. One popular board is the https://www.crowdsupply.com/krtkl/snickerdoodle
92.
by rphlx 9y ago
> publication bias – the tendency for positive but not negative results to be published Many years ago Feynman expressed concern and regret about the harm that causes to experimental physics . One can imagine it being a far bigger issue
93.
by rphlx 9y ago
It does not totally invalidate the benefits you mentioned but from what I've heard there are mature commercial services that map consumer IPs to meatspace IDs (name, phone number, address, household income, credit score, etc). The ad i
94.
by rphlx 9y ago
Note though that once the market is majority passive - which seems likely within the next decade - it actually is theoretically possible for active to slightly outperform passive.
95.
by rphlx 9y ago
They are clearly in an unenviable position but I think they would have come off better with a more honest, direct acknowledgement of the failure of a tertiary objective, rather than that "oh noes, might derail the emotive hype-train, l
96.
by rphlx 9y ago
I would have agreed with you about very poor SRAM scaling until very recently; it looks like 10nm/"7nm" made some decent progress there at last, though nothing like The Good Old Days when it actually scaled close to what the
97.
by rphlx 9y ago
To clarify my point: an AMD64 CPU could still run in 32-bit mode, if the customer preferred. Much later, the x86_32 ABI work also retained small pointer sizes while providing additional benefits. Whereas there is no way for a customer to fu
98.
by rphlx 9y ago
I agree there is a good chance they will lose a material share over the coming 1-2 years to epyc, but at the moment, the x86_64 server market is almost 100%-Intel.
99.
by rphlx 9y ago
May not be a winnable argument on HN (where the consensus seems to be that this is nearly-100% Intel's fault), but I think a significant fraction of the blame properly belongs on their customers, particularly their multi-tenant public
100.
by rphlx 9y ago
> Intel may never ship them before switching to MCM Fantastic claims require fantastic evidence.. history shows that there are many ways of fixing or designing-around manufacturing yield problems. Do you have any actual evidence that the
101.
by rphlx 9y ago
I agree with your general thrust though I think you are overstating a few points significantly. > Skylake has born SIX new product lines; Goldmont, Goldmont Plus Goldmont, Goldmont Plus are Atom products and are not "Skylake-derived
102.
by rphlx 9y ago
> a medium of exchange that doesn't use absolute units, but is a function of your ability to pay. This is already implemented in many areas of modern life, especially by governments (Obamacare, progressive taxation, social security,
103.
by rphlx 9y ago
I agree with your basic point - a generic syscall batching mechanism would be a good thing - but it's worth noting that GPU workloads are usually much better suited for ginormous "fire and forget" command/command+data se
104.
by rphlx 9y ago
> I'm not sure why people think electronics would be an exception I'll take a swing at this.. one reason is that modern electronics contain - both directly and through remote access to other systems via stored cookies, etc - fa
105.
by rphlx 9y ago
> they'd never have even dreamed up Side channels in general have been known for a long, long time in mil and intel communities, so it is likely that folks there long ago identified and understood that it's a bad idea to share
106.
by rphlx 9y ago
> need "execute JS" to be an explicit per-site permission I would personally like that, but it's too optimistic to think that the average user would gain much security from it. Most of them will discover that things work f
107.
by rphlx 9y ago
Yes. I doubt this will be what actually happens, but perhaps the safest fix is to remove speculative execution in its entirety, increasing clock frequency and/or core count to mitigate the resulting performance loss by as much as possi
108.
by rphlx 9y ago
Well, web pages that have a legit need for higher res could request it in the same way that webcam or location access is requested today.
109.
by rphlx 9y ago
Did they note any change in attack duration or success rate with that vs a high-res HW counter?
110.
by rphlx 9y ago
That's a fair point, but let me note that it is still less desirable (to an attacker) than the TSC in at least one case: when system load is high enough that there are other non-attacker-controlled threads running on the same core. Whe
111.
by rphlx 9y ago
It's likely they could disable speculative execution in its entirety, either in ucode or UEFI, but that would harm many compute-intensive workloads by 5-10% or more, so my guess is that somebody decided to push this page table mitiga
112.
by rphlx 9y ago
> crippling all userspace applications seems like going too far. Depends on the system IMO. I certainly want the TSC when I'm profiling something highly-performance-sensitive on my workstation. Yet I am hard-pressed to see why any u
113.
by rphlx 9y ago
There are other side channels where an attacker cannot cause the desired operation to be repeated thousands or millions of times back-to-back.. If Alice performs an operation only once, and it leaks sensitive data through a timing variati
114.
by rphlx 9y ago
> adding random noise just makes attacks take longer No. It's true that with a low-res clock source in some cases an attacker can still get the precise measurement they're after by repeating an operation 1000x+ more times. In s
115.
by rphlx 9y ago
> we are disabling or reducing the precision of several time sources I am really happy to see this happening at long last. One can argue that almost every x86 SW side channel attack (Spectre and many prior ones that, for instance, leak
116.
by rphlx 9y ago
That's correct as I understand it, though there is a risk that some high-profile event will cause the media to whip up enough (understandable) public outrage to cause the SEC to actually, reluctantly fine someone for that.
117.
by rphlx 9y ago
The DRAM mfgs did respond to some extent & it is much harder - though perhaps not entirely impossible - to RH DDR4.
118.
by rphlx 9y ago
It has nothing to do with AVX AFAICT. They are going to set X86_BUG_CPU_INSECURE [1] on all public Intel CPUs, including old ones that lack AVX (Core2, etc). [1] I do hope they rename that flag to something like X86_BUG_NEEDS_PTI as the cur
119.
by rphlx 9y ago
I certainly agree that there are still errors, wheel slip being a major one. However, that does not cause an accumulating/ever-compounding error in speed nor distance travelled in the way that, say, a one-time error from an IMU's
120.
by rphlx 9y ago
> probably runs into issues with accumulated error Typically there's no single nor double integration required for a wheeled ground vehicle; distance (revolutions times wheel circumference) is the primary measurement, with speed bei

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