rep_lodsb

42 ms·

541.
by rep_lodsb 5y ago
Win9x also uses DOS as a boot loader :)
542.
by rep_lodsb 5y ago
As you observed before, real mode is also privileged. Both before and immediately after enabling protected mode, the code segment you are running from is already "ring 0" (even if it wasn't loaded from a GDT descriptor), and
543.
by rep_lodsb 5y ago
>Do we leave real mode as soon as CR0 bit 1 is set Yes, that's what the bit is defined as doing. Protected mode was introduced on the 16-bit 80286, and 16-bit code segment descriptors are still supported to this day. Even in real mo
544.
by rep_lodsb 5y ago
The point is that the CPU might still be in real mode at the point in time when the far jump is decoded, and thus execute it with real mode semantics. Coding a seemingly useless near jump was the way to prevent that. Whoever wrote the moder
545.
by rep_lodsb 5y ago
This probably no longer applies in any way to modern processors, but the 286 and 386 did have a "prefetch queue" (containing opcode bytes fetched from CS:eIP), as well as a "decoded instruction queue". Up to 3 instructio
546.
by rep_lodsb 5y ago
https://nethackwiki.com/wiki/Schroedinger%27s_Cat
547.
by rep_lodsb 5y ago
IMO the concept of free will doesn't make sense, at least not without also believing in the existence of a soul. If you were to make a decision that is not in some sense pre-determined by the structure of your brain (as shaped by biolo
548.
by rep_lodsb 5y ago
I have an idea of how to keep control of interrupts without needing all the complexity of V86 mode: relocate the IVT! On 286 and above, the interrupt vectors always start at the address in the IDTR (interrupt descriptor table register), ev
549.
by rep_lodsb 5y ago
386 may be a bit too far, but there was a high resolution shot of an 80286 on the visual6502.org wiki (now sadly offline), were you could almost read the microcode ROM visually. I spent a lot of time staring at that and got at least a goo
550.
by rep_lodsb 5y ago
You are correct, and the other one is AVAILDEV. Set it to false, and device names like CON only refer to the device when prefixed with "/dev/". Microsoft did have a reason to remove these features: compatibility with b
551.
by rep_lodsb 5y ago
It became Real/32. Too bad the 286 version (using LOADALL to virtualize real mode) doesn't seem to be available anywhere, would be fun to see how it actually performed...
552.
by rep_lodsb 5y ago
DOS 2.0 was originally supposed to be a single-user version of Xenix. There were some undocumented options to make it more Unix-like, which were removed in later versions: https://www.youtube.com/watch?v=Vo8NG8T4rWs The con
553.
by rep_lodsb 5y ago
As long as the hardware isn't DMA-capable or has to be shared, allowing programs direct access isn't a security violation . Since everything runs in protected mode, the kernel is still "in charge", and can limit what I&
554.
by rep_lodsb 5y ago
Are you sure? I don't think any NT kernel allowed userspace code to directly access I/O ports. The earliest versions didn't even let graphics drivers do that, but that was changed (in either 3.51 or 4.0?) for performance reas
555.
by rep_lodsb 5y ago
"Stringly typed" programming gave us SQL injections, shellshock, and the log4j debacle. Not to mention probably 99% of processor cycles being wasted on parsing and re-encoding again and again from/to text-based formats that a
556.
by rep_lodsb 5y ago
Yes, it was moderately anti-diversity. But many people reacted as though it did say something like "women belong in the kitchen". Okay, it's been some time since I read the document, and there may have been parts that weren
557.
by rep_lodsb 5y ago
I know that, but this one ("Iotel") either has a bit-flip or is some kind of fake?
558.
by rep_lodsb 5y ago
What's "GenuineIotel"? Did an actual processor report this ID?
559.
by rep_lodsb 5y ago
On older x86 chips - anything before the 486 - there was no cache, but opcode bytes were prefetched into a queue, ranging from 4 bytes (on the 8088) to 16 bytes on the 386. The 286 and 386 had an additional queue holding up to 3 decoded ins
560.
by rep_lodsb 5y ago
That doesn't mean we should eliminate everything else. Many operations that would require 3 or more simple instructions are easy enough to implement in hardware, so that they take no more time than one of these simple instructions. Thi
561.
by rep_lodsb 5y ago
Carry flag and overflow checking? We don't need those things because C doesn't support it! That sadly seems to be the kind of thought process behind RISC-V, and a lot of other "modern" computing: Everything should be wri
562.
by rep_lodsb 5y ago
It should be easier for the processor to detect xor-reg-with-itself as a special case. Intel has documented this as the preferred instruction to use since the Pentium afaik.
563.
by rep_lodsb 5y ago
One could get rid of the push / pop though, assuming that the high bits of EAX don't need to be saved: movzx eax,al ;could also do "and eax,0ffh" mov al,[rbx+rax]
564.
by rep_lodsb 5y ago
username related - read lots of stuff while doing nothing useful with it :) other fun x86 ones: CALL SP will call whatever code has been pushed on the stack. Unlike PUSH SP, it works the same on 8086 and newer CPUs RET -2 (16 bit; -4 or -8
565.
by rep_lodsb 5y ago
>I guess an alternative solution would be to put the stacks in different address spaces somehow, but that could get very complicated (now you have two kinds of pointers). Are there any old systems that had separate heap and stack address
566.
by rep_lodsb 5y ago
Okay, had to register just because of the positive comments so far. I know nearly nothing about machine learning and may be a bit biased, but has anybody actually read the paper? As I understand it, the model is trained on what compilers do