prabhu-yu

8 ms·

31.
by prabhu-yu 3y ago
Agree, Any reason why is the Type-C not used?
32.
by prabhu-yu 3y ago
Repo Link: https://github.com/eborin/riscv-programming I may be wrong. I am not able to see the content of the book. (I thought, above repo has the content.). More ever, I see copyright notice in the book. So, it is op
33.
by prabhu-yu 3y ago
About protection: I see book is in github as a public repo. I will try to print with my pdf tools. Please give me some time.
34.
by prabhu-yu 3y ago
Did you try print to pdf in browser?
35.
by prabhu-yu 3y ago
I understand you. I had same thoughts. Yet I posted this because- - Book is really good for learning RISC-V Assembly. - There are plenty other RISC-V simulators. Use what you like. For learning each instruction one by one, I like the follow
36.
RISC-V Assembly Programming(riscv-programming.org)
97 points by prabhu-yu 3y ago|21 comments
37.
Show HN: MicroPython RPI Pico- Enabling Double Precision Float(github.com)
1 points by prabhu-yu 3y ago|0 comments
38.
by prabhu-yu 3y ago
I think, Python Dictionary format can represent structured data well. i.e., I need to re-present some data, I use Python dictionary format, then YAML, then JSON. Possibly never in XML as I feel the tags simply redundant, verbose, prone to
39.
Milk-V Duo: A $9 RISC-V Computer(milkv.io)
199 points by prabhu-yu 3y ago|120 comments
40.
by prabhu-yu 3y ago
This is my understanding - - A powerful alternative to Rpi-Zero/Rpi-pico. - When we don't need wireless i/f, it makes even more sense. - Compared to Rpi-pico, where we can't run OS, here we can. - Compared to Rpi-z
41.
How_to_write_sane_C++(gabarro.org)
3 points by prabhu-yu 3y ago|0 comments
42.
Ask HN: Why did not USA safely brought down the Spy Balloon?
2 points by prabhu-yu 4y ago|15 comments
43.
by prabhu-yu 4y ago
Do not worry too much on running ARM or x86-64 or mips binary on RISC-V. You will soon start cross compiling the source code to the target architecture. Running the binary of other arch to another is temporary solution. Rather we need to th
44.
by prabhu-yu 4y ago
How about Scons? I feel, Scons is much simpler even if it less efficient in speed of compilation. Please comment.
45.
RISC-V Foundational Associate (RVFA) Certification(training.linuxfoundation.org)
2 points by prabhu-yu 4y ago|0 comments
46.
by prabhu-yu 4y ago
Thank you for sharing this. I was not aware of this. But now agree, it is indeed portable solution.
47.
by prabhu-yu 4y ago
Thank you for the respone. Can we write like this? Klass ssc __attribute__((64)); This could convey more info than padding. Further, I wish, gcc could have provided an attribute that explicitly forces for the cache line alignment than just
48.
by prabhu-yu 4y ago
In the fix, they have padded. instead of padding, do we have compiler directive, that forces the a variable starting using a fresh cache line (instead of putting it in the last cache line?) Reason I am asking this, it will make the fix inde
49.
by prabhu-yu 4y ago
Thank you, I will study more.
50.
by prabhu-yu 4y ago
In C++, there is Move semantic. If we use "Move semantic" in C++ code, could it match the memory safety of the Rust?
51.
by prabhu-yu 4y ago
(I may be wrong here.) Using Thonny IDE, I can just read all Python scripts stored in QSPI Flash. At least, I could not find how BOOTSEL will help here. QSPI Flash is external to RP2040. I was expecting some form of facility to encrypt XIP
52.
by prabhu-yu 4y ago
Pico does not have flash Protection/Lock. This makes impossible to protect the firmware. Almost every other uC has a feature to disable reading of flash content. Any comments on this?
53.
by prabhu-yu 5y ago
Should the question be like this? "Can a program ~~allocate~~ use more memory than is physically available on the server (assuming no swap)?" Because, malloc allocates from virtual memory, not from the physical memory. Only when w
54.
by prabhu-yu 5y ago
Are you sure, this does not have the GIL? I tried looking into documentation, I could not find such info. Can you please point the link?
55.
by prabhu-yu 5y ago
Ok, can we do this? Python interpreter can understand if it is running on 1 core processor (assume 1 core = 1 HW thread) or multi core processor. Then use GIL taht suits. ie, if the code uses multiple SW threads, use GIL that suits needs...
56.
by prabhu-yu 5y ago
Yes, I too confused on the same points you mentioned. Thanks for clarification.