pm215

73 ms·

781.
by pm215 9y ago
As a UK citizen, I find that when I see armed police it is inherently intimidating, because the cultural expectation is that police are unarmed and so it represents a massive escalation. (Seeing them in the UK is becoming more common these
782.
by pm215 9y ago
Mmm. If you want an example of a console that seemingly was never meant to be used for real work, try the old Sun SPARCStation Solaris consoles. Those were implemented using the boot PROM's graphics drivers which were written in Forth
783.
by pm215 9y ago
Not all CPUs do register renaming, and almost all architectures will have started out being defined for a CPU which didn't do renaming. Even today, lower end CPUs (think the embedded market) don't do register renaming. If you want
784.
by pm215 9y ago
No, I'm doing what I would classify as "normal" developer work. Negotiation: I have had (on a sample size of 1) no luck getting this at initial employment, but I have managed (sample size of 2) to arrange it after working som
785.
by pm215 9y ago
Working four days a week. Effectively I pay 20% of my salary to buy an extra non-working day every week. This is a massive QoL improvement (a) because it keeps my RSI from being unbearable and (b) because of all the fun stuff you can do wit
786.
by pm215 9y ago
Even today, allowing unaligned accesses is still not free -- there is an implementation cost in transistors and in design complexity. There's a tradeoff here, as usual. There are a lot of places with a CPU architecture where there&#x27
787.
by pm215 9y ago
Alignment requirements are and have historically been very common -- you can see them on the PDP-11, the 680x0, and so on. It's only because a few very popular architectures like x86 have had very loose or no alignment requirements tha
788.
by pm215 9y ago
For 64-bit ARM (AArch64), load-exclusive/store-exclusive and load-acquire/store-release require aligned addresses. (Seems reasonable to me, trying to handle atomic accesses to aligned data is no fun). You also get a fault for any
789.
by pm215 9y ago
The answer to "why not always put it on the stack" is "because a lot of functions are leaf functions and so always writing it to the stack is making every function pay the memory access hit rather than just the ones that need
790.
by pm215 9y ago
These are, or used to be, quite common with gcc. Unused-result warnings require dataflow analysis to run to determine whether the values are used, and on no-optimisation compiles gcc didn't bother to do dataflow analysis. Conversely, h
791.
by pm215 9y ago
In this particular instance, 64-bit ARM (A64) has a conditional-set instruction, so "int cmp(int x) { return x < 32; }" compiles straightforwardly to "cmp w0, #0x1f; cset w0, le; ret". For 32-bit ARM you can use the
792.
by pm215 9y ago
A quick google suggests this was true for the Cortex-A8 (released in 2005, over a decade ago), but is unlikely to be true for any implementation since, and I would definitely not expect it to be true for a modern 64-bit implementation like
793.
by pm215 9y ago
Well, the microcode for AND is simple; it's this line G17: L_ ACDEST AND T, TASK, :SHIFT; ...the problem is that that's in the middle of the decode (there's a computed jump into this lot from the line labelled DIS1:). So you
794.
by pm215 9y ago
If you like that kind of thing and happen to be visiting Tokyo, the Daimyo Clock Museum is worth dropping into. It's a little one-room museum with a couple of dozen old clocks that implement that variable-hours setup, some of them runn
795.
by pm215 9y ago
Interesting idea and it would certainly help to alleviate the "how many editors do we need to provide code style config for" problem, but it looks rather limited in scope at the moment (for instance it doesn't even try to add
796.
by pm215 9y ago
IME the problem with applying rr to a flaky test is that it's not uncommon that rr will just reliably and deterinistically cause the test to not fail. This is especially true for failures due to multithreading bugs and similar race con
797.
by pm215 9y ago
Decades of experience teach us (1) that the great mass of buggy C code is simply not going away, and the best we can hope for is that it dwindles into more niche situations (compare Fortran and COBOL: those codebases haven't gone away
798.
by pm215 9y ago
"faster than QEMU" isn't a particularly high bar to clear, though. In particular if you're only emulating a single process rather than a full guest OS then you can reduce the overhead quite a bit. Plus if you design some
799.
by pm215 9y ago
I (and the people I know) write resignation letters because it makes the intention clear (I really am resigning, not just sounding off because I'm annoyed or discussing possibilities). It also gets the facts down in writing in case of
800.
by pm215 9y ago
The instruction set reference (the architecture manual, to give it its proper title) has been freely available from ARM for some time, though you needed to create a website account and agree to a clickthrough license. It's more recent
801.
by pm215 9y ago
ARM and Thumb are just different encodings of the same instructions, mostly. Having switchover be done implictly via branch instructions is convenient for interworking -- you can link an ARM library with a Thumb application and it all just
802.
by pm215 9y ago
Using String as an example error type seems like a bad choice if nobody actually uses it in practice, though -- it's just leading you down the garden path. Personally I found the error handling section of the documentation confusing an
803.
by pm215 10y ago
Also non-ancient ARM chips add the movw and movt instructions so you can load a 32 bit constant simply in 2 insns rather than having to play games with sequences of arithmetic insns or use a constant pool.
804.
by pm215 10y ago
Bear in mind that 'Cortex' covers every modern ARM chip right the way from a tiny (~12,000 gates) microcontroller like the Cortex-M0 up to high performance 64 bit designs like the Cortex-A73, so it isn't a label that tells yo
805.
by pm215 10y ago
> ~1/3 of people stuck the wrong end into their thing Ow...
806.
by pm215 10y ago
My point is that the spec does not give the behaviour-to-machine-instruction mapping, only the other way round, and reversing the mapping is non-trivial. Table driven assemblers and disassemblers would be straightforward to produce from t
807.
by pm215 10y ago
I don't see how you could generate a compiler backend from this -- the spec/pseudocode give you the "this instruction has these effects and side effects" mapping, but you can't easily reverse that to get the "i
808.
by pm215 10y ago
It just seems to me that the window is small (and you have to write a weaponised exploit in that time too), and the only people likely to be able to reliably intercept the email are nation-state actors who do bulk email slurping, and they&#
809.
by pm215 10y ago
Advertising that you use pgp and then in practice not using it is kind of daft, but is there actually much benefit to using encryption to initially report vulnerabilities?
810.
by pm215 10y ago
Wikipedia reckons 10-20 cycle penalty for a branch mispredict (which sounds plausible given it fills the pipeline with useless junk). Given that branches are quite common, that's painful enough to want to avoid, but definitely not so p

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