phire

19 ms·

211.
by phire 10mo ago
I'm not sure that reporting is correct. Micron have EOLed a bunch of ddr4/lpddr4 parts, but that happens all the time, even to current nodes. There are still plenty of LPDDR4 parts in Micron's catalog [1] that are not EOL. TB
212.
by phire 10mo ago
Problem is that I don't think LPDDR5 comes in any sizes smaller than 1GB, so if they want to stick to the current 512MB spec (and price point), LPDDR4 might be the way to go. It might be nearer to EOL, but it's not actually EOL an
213.
by phire 10mo ago
And IBM were planning for the PS3's cell processor to run at like 6ghz, with later versions scaling further. Though, it's not like Sony were planning to ship the PS3 clocked that high, they were just expecting their 3-4ghz cpu to
214.
by phire 10mo ago
It never stopped. Just takes backwards steps from time to time with major architectural innovations that deliver better performance at significantly lower clock speeds. Intel's last backwards step was from Pentium 4 to Core all the way
215.
by phire 10mo ago
The 512Mb RAM die actually embedded into the same RP3A0 package as the CPU (it's the exact same CPU die used in the Raspberry Pi 3). So the stock is exactly the same world wide and linked. and I'm pretty sure the RP3A0 chips are p
216.
by phire 10mo ago
I mean, it was one of those inevitable technologies. Other companies had already invented the CCD, it was only a matter of time before someone would digitise the signal and pair it with a storage device. It was an obvious concept. All Kodak
217.
by phire 10mo ago
It seems to be more that they are simultaneously launching and killing the product. Sounds like they entered into a contact to develop and sell the CM0 to several large manufacturers who happen to all be in China, hence the launch. But then
218.
by phire 10mo ago
MobyGames [1] claim they are unique missions. More or less the same story, but different maps, objectives and briefing text. Maybe I need to re-download it, and check out the differences. I remember playing those six missions so many times
219.
by phire 10mo ago
Yeah, 9 patches for the original game, then the Battle.net Edition in 1999 (which added support for TCP/IP networking and Battle.net matchmaking), and at least one downloadable patch for that. https://warcraft.wiki.gg/w
220.
by phire 10mo ago
There aren't really any "systems programming" platforms anywhere near production that doesn't have a workable rust target. It's "embedded programming" where you often start to run into weird platforms (or
221.
by phire 10mo ago
I hate the product. But as a business staggery for Boom Supersonic, it kind of seems like a good idea. They get a (hopefully short term) revenue stream, and a whole bunch of "real world" testing on their engine core.
222.
by phire 10mo ago
Woz was almost certainly there when ADB was created. It's documented that he was quite involved in the design of the Apple IIGS. And ADB was created for the IIGS (right?) But that doesn't quite mean he was involved in the design o
223.
by phire 11mo ago
The zero register helps RISC-V (and MIPS before it) really cut down on the number of instructions, and hardware complexity. You don't need a mov instruction, you just OR with $zero. You don't need a load immediate instruction you
224.
by phire 11mo ago
It spends it's entire mission above the Kármán line (100km), so it is legitimately in space, and is therefore a spacecraft, like all other satellites.
225.
by phire 11mo ago
This video covers the general concept, and even mentions redwire at the end Air Breathing Satellites in Very Low Earth Orbit (13:12) - Eager Space : https://www.youtube.com/watch?v=vEfatzhHhvg
226.
by phire 11mo ago
"7k cycles at four flights/day" It wasn't doing four flights per day. As a long-distance cargo aircraft it was doing two flights per day, and I doubt it was flying every single day of the week. So we are talking about
227.
by phire 11mo ago
Jazelle worked for its target market (or at least, I've never seen anyone claim otherwise). But its target market wasn't "faster java". Instead Jazelle promised better performance than an interpreter, with lower power dr
228.
by phire 11mo ago
I think I'd prefer a compile-time guarantee. Something that allows me to tag annotate a function (or my whole crate) as "no panic", and get a compile error if the function or anything it calls has a reachable panic. This wi
229.
by phire 11mo ago
Yes, but they are reasoning within their dataset, which will contain multiple example of html+css clocks. They are just struggling to produce good results because they are language models and don’t have great spatial reasoning skills, becau
230.
by phire 11mo ago
Most image models are diffusion models, not LLMs, and have a bunch of other idiosyncrasies. So I suspect it's more that lessons from diffusion image models don't carry over to text LLMs. And the Image models which are based on mul
231.
by phire 11mo ago
My WH-1000XM5 set broke, and it was going to cost more to repair it than buy than simply buying a new pair. So I decided to check out the cheaper end of the market, and bought a pair of Edifier W830NB. They are pretty decent (notable downg
232.
by phire 11mo ago
I believe this has already been fixed by LE audio. But support (on both ends) is quite rare, experimental, and needs to be explicitly enabled.
233.
by phire 11mo ago
If the goal is simply to make social media unprofitable, you can just be really brutal and require that all users from a language region visiting a website (or using an App) must be delivered the exact same set of ads. The fact that most ad
234.
by phire 11mo ago
Only problem with that approach is that assume_init() is unsafe (because it depends on you getting the initialisation loop correct), and many people are (correctly) hesitant to use unsafe. IMO, it would be really nice if the naive syntax
235.
by phire 1y ago
Yeah, it panics when you use after free. [1] But I'm not sure it's worth porting your code to Fil-C just to get that property. Because Fil-C still needs to track the memory allocation with its garbage collector. there isn't
236.
by phire 1y ago
Motor rotation isn't quite enough, as it's not aligned to the sectors on the disk. Drives which do skip indexing (Like Apple's Disk II) use the actual data on the disk for indexing. Each sector header has a track/sector&
237.
by phire 1y ago
Everything it says about cache coherency is exactly the same on ARM. Memory ordering has nothing to do with cache coherency, it's all about what happens within the CPU pipeline itself. On ARM reads and writes can become reordered withi
238.
by phire 1y ago
I’m of the opinion that it’s unlikely to happen within 50 years. But I still think it’s a good idea to start switching over to post-quantum encryption, because the lead time is so high. It could easily take a full 10 years to fully implemen
239.
by phire 1y ago
I'm not against adding new instructions. I love new instructions, even considered trying to push for a few myself. What I'm against is the idea that it's easy to add instructions. Or more the idea that it's a good idea t
240.
by phire 1y ago
The question is not so much when the first CPU ships with the instruction, but when the last CPU without it stops being relevant. It varies from instruction to instruction, but alternative code paths are expensive, and not well supported by

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