phire

32 ms·

541.
by phire 2y ago
I was confused as to why a compiler might do that. Surely a jump to register would always be faster than writing it out to memory. Then I remembered we are probably talking about 16bit code (for Win16), and that far pointers were a major th
542.
by phire 2y ago
I don't think I ever got below 64kps in my own testing before the audio quality fell apart. I was using a Palm PDA, so I found a player that supported ogg. That allowed me to push to 48kps (or maybe even 32kps) with "acceptable&qu
543.
by phire 2y ago
I love reading about optimised Discrete CPUs like this. Only 16 logic ICs. Doesn't even have an adder, the only ALU function is a 1 bit Nor gate. Details on this page: http://mynor.org/my4th.htm
544.
by phire 2y ago
> Not having loop handling does seem off I do agree. The fact that those uop queues are already there and Intel isn't using them as a loop buffer does make me ask questions. Have they just not gotten around to it? Have they decide
545.
by phire 2y ago
Intel are probably using a TAGE style predator along the lines of ITTAGE or COTTAGE from http://www.irisa.fr/caps/people/seznec/JILP-COTTAGE.pdf These predictors change their prediction (both direction and de
546.
by phire 2y ago
I'm pretty sure the patten of allowing the branch predictor to run ahead is pretty common. At least, it's common to have multi-level branch predictors that take a variable number of cycles to return a result, and it makes a lot of
547.
by phire 2y ago
There seems to be a very common misconception about branch prediction, that its only job is to predict the direction of the branch. In reality, the problem is so much deeper. The instruction fetch stage simply can't see the branch at a
548.
by phire 2y ago
> Tight loops come from the uop cache, and branchy code gets 3-way decoding. First, there is no uop cache on the "mont" cores. Second, Intel aren't decoding both sides of the branch. That wouldn't actually help much
549.
by phire 2y ago
You are right. Goldmont Plus isn't really interesting as a product. Even its power efficiency wasn't that good at the time, you were better off with a two core ULV Skylake part. And so you only really found it in really cheap use
550.
by phire 2y ago
> The decision to go for two tiny cores rather than one beefier core with an FPU was strange It's very useful to dedicate an entire core to running your timing-critical assembly code, and only run higher level non timing critical
551.
by phire 2y ago
> Wouldn't be surprised if they licensed the hardware block from RSA. The only hardware crypto blocks the Wii had were SHA and AES, there wasn't a hardware RSA block. Which makes sense, it had to run both SHA and AES over la
552.
by phire 2y ago
This is what my grandfather was like for several days after he had a stroke. No short term memory, but he was very lucid and sharp. When the nurses asked their standard questions ("do you know where you are", "do you know why
553.
by phire 2y ago
I don't think we can rule it out. The current universe conditions have existed for about 12.8 billion years, and while it might have taken 4.5 billion years for vertebrates to evolve on earth, other planets might have taken faster path
554.
by phire 2y ago
AGP is little more than a second PCI bus running at higher clock speeds. Because PCI was a shared bus, not only did the video card have to share bandwidth with every other card, but PCI ended up stuck at the original 33mhz speeds of the fir
555.
by phire 2y ago
First, GameCube/Wii API actually generates the "shaders" at runtime, so there is simply no way to know which vertex/pixel pipeline states the game needs short of playing though the whole game, looking at every single bit
556.
by phire 2y ago
> so I'd expect removing the frontend to be a decent win I did some testing before working on ubershaders, and my modified build which cached the bytecode output of FXC/D3DCompile (whatever dolphin was using at the time) didn
557.
by phire 2y ago
The only step that SPIR-V replaces is parsing the GLSL to an AST tree, and that's only a small part of the total time to compile a shader. Usually the bottleneck is Register allocation or scheduling. Back when Vulkan was developed, the
558.
by phire 2y ago
DCC doesn't work through NAT, as it creates a fresh connection to a random port. That's the entire contents of the DCC send message, the ip/port of the sender and the filename. I'm pretty sure these Netgear routers were
559.
by phire 2y ago
Extremely common misconception (even among developers on those platforms) In reality, the OG Xbox and GameCube GPUs are almost identical in pixel shading capabilities (Though the gamecube's vertex shading pipeline is legitimately fixed
560.
by phire 2y ago
> The Xbox could only load textures as the starting instructions before doing math and tried to make up for that with a few "do very specific math and load textures in a single instruction" ops. If you look closely, the TEV a
561.
by phire 2y ago
Has it really been 9 years since I started working on Ubershaders? I'm a little surprised no better solution has come along. Vulkan didn't even exist back then (and DirectX 12 had only just released) but instead of making things b
562.
by phire 2y ago
That's a very old rumour. I first heard it 9 years ago, as a rumour for the upcoming Skylake uarch [0], based on an intel paper from 2012 [1] For that reason, I'm inclined to dismiss it without too much thought. And the general in
563.
by phire 2y ago
Yeah, that's a good question. However, I'm not sure the size comparison of Zen4c to Zen4 is very useful, because AMD didn't just optimise Zen4 for performance, they also optimised it for an earlier release date. My understand
564.
by phire 2y ago
> I would really like to learn how to apply the pseudo-3d or 2.5d methods that were used by Microprose in F-19 Stealth fighter. F-15 is not pseudo-3d at all. Flight simulators were early innovators in proper polygon based graphics. Partl
565.
by phire 2y ago
Most people focus on Intel's P6 derived line of uarches (Golden Cove, Redwood Cove), because those are the cores with the highest performance. But I think the atom derived "mont" line (Gracemont, Crestmont) is much more inter
566.
by phire 2y ago
I find it interesting they had an explicit "flat trapezoid" primitive (slide 14). By flat, I mean it only supports trapezoids where the top and bottom edges are flat, aligned with the y grid. I'm not aware of any GPU that exp
567.
by phire 2y ago
I've always assumed he has a large backlog of comics, and a script that pushes them out on schedule. He can always push new comics into the queue based on current events or fresh ideas, but at other times he can probably go for weeks w
568.
by phire 2y ago
It had wheels and it can move. But only with traffic shut down.
569.
by phire 2y ago
I guess it's theoretically possible to engineer a bridge that can move with traffic on it. But this bridge is engineered with solid feet for taking traffic loads. The wheels are only extended for movement and wouldn't be able to t
570.
by phire 2y ago
> This optimization is only possible for store-based systems since the set of shared libraries is fixed and immutable. In a traditional Linux distribution, each shared library could be updated at any time, which would invalidate the cac

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