phire

26 ms·

421.
by phire 2y ago
Ok... the only thing that go version directives do is selectively enable new features. Essentially, they are only really there to help you ensure your code will continue compiling in older versions of the compiler. Hell, until recently it w
422.
by phire 2y ago
No. The point of rust editions is that they do break support for older code, which is very different to what go has now settled on. IMO, it's the best of both worlds. Old code continues to work forever, but your language design isn&#x2
423.
by phire 2y ago
The the introduction of Python 3 wasn't a mistake. The mistake was discontinuing Python 2. Just look at how rust does it. Rust 1.0 code still works in the latest version of rustc, you just need to set the project to the Rust 2015 editi
424.
by phire 2y ago
Not even reference counting. There are no references as values are always cloned (or moved).
425.
by phire 2y ago
Yeah, should be easy enough to filter these particular jumps out. It's an obfuscation designed to annoy people using common off-the-shelf tools (especially IDA pro) Most obfuscations are only trying to annoy people just enough that the
426.
by phire 2y ago
3-4 uops per cycle is more of an average throughput than a typical throughput. The average is dragged down by many cycles that don't decoded/rename any uops. Either waiting for bytes to decode (icache miss, etc) or rename is block
427.
by phire 2y ago
> The fact that Intel managed to get them lined up for small loops to do 9x effective instruction issue is basically miraculous IMO Not just small loops. It can reach 9x instruction decode on almost any control flow pattern. It just lo
428.
by phire 2y ago
Or they started the APU, but never got around to connecting its generator to the main bus. That's a second button press, after confirming it has successfully started.
429.
by phire 2y ago
> However that's already available from radar, ADS-B Not in this case. ADS-B was lost at the same time as the flight recorders. If there was a primary radar in range, they might be able to recover groundspeed and a 2d flight path
430.
by phire 2y ago
Tying buses together is a manual operation. All indications are that the pilots didn't have enough time to get that far in the checklist. It's also not that important to restore AC power. The standby bus automatically brings the s
431.
by phire 2y ago
Because "the event" was the bird strike, and 4 minutes before the crash is the right timeframe for that. At least one of the engines was hit, and they appear to have lost AC power. The crash on the second landing attempt is just a
432.
by phire 2y ago
No. Prey was one of the first games to hype portals and non-euclidean maps for gameplay. Portals for rendering date back to the dawn of 3d graphics and many early FPS engines used the concept. But these portals were only there as a renderin
433.
by phire 2y ago
And that's a problem with human expectations not lining up with the reality of LLMs. You could actually implement such functionality with current LLMs. Even one small enough to run on a phone. But you can't implement it well enoug
434.
by phire 2y ago
It's not related to the size of the model. It's more of a prompting/design issue. The LLM has been told to summarize the message, not to identify it as a scam or not.
435.
by phire 2y ago
It's apparently all EEVEE.
436.
by phire 2y ago
I haven't read though the whole thing, but my rough understanding is: - A ray tracer runs on the CPUs, and generates surfels (aka splats) - The surfels are uploaded to the GPU - Then the GPU rasterizes the surfels into a framebuffer (a
437.
by phire 2y ago
We there are two different things here. The custom CPU rasteriser (Star Machine) that pushes 4k 120hz is mentioned in the intro, but the implementation of spline-based terrain covered by the article is just a prototype developed in blender.
438.
by phire 2y ago
It's a parody. The whole genre of clicker games is a parody to start with, but this is more parody than most.
439.
by phire 2y ago
Yeah, "incorrect PRF read" is something that might exist. I know modern CPUs will sometimes schedule uops that consume the result of load instruction, with the assumption the load will hit L1 cache. If the load actually missed L1,
440.
by phire 2y ago
Seems rather pointless to implement it like that. You would save space in the scheduler because the uops have been fused, but execution time and execution unit usage is the same as just executing the original ops before this optimisation wa
441.
by phire 2y ago
The speculation of a "reg + 10-bit offset" representation feels wrong to me. That requires a whole bunch of extra 64-bit full-adders everywhere one of these pairs might be consumed (so realistically, on every single read port of t
442.
by phire 2y ago
The 3 cycles latency casts massive suspicion on the bypass network. But I don't see how the bypass network could be bugged without causing the incorrect result. So the scheduler doesn't know how to bypass this "shift with sma
443.
by phire 2y ago
> 4. The 3-cycle case occurs when the physical register read cannot be optimized away?? No... the 3-cycle case seems to be when the physical register read is optimized away. I think it's some kind of stupid implementation bug.
444.
by phire 2y ago
Ok... That does make some sense. Essentially, Intel have allocated a bunch of fake renaming registers to hold all small immediates. Like how MIPS had a zero register, Intel now have over 1000 constant registers. These registers don't r
445.
by phire 2y ago
You mean the early systems like the IRIS 2000? It arguably fits, because it pairs a 68010 with hardware accelerated 3d graphics. As far as I can tell, it's not quite modern 3d graphics. If you paid for the geometry engine, you did get
446.
by phire 2y ago
Intel had a leading line of ARM SoCs from 2002-2006. Some of the best on the market for PDAs and smartphones. Their XScale SoCs were very popular. But Intel gave up and sold it off, right as smartphones were reaching mainstream.
447.
by phire 2y ago
More explicitly. In 2006, Apple asked Intel to make a SoC for their upcoming product... the iPhone. At the time, Intel was one of the leading ARM SoC providers, their custom XScale ARM cores were faster than anything from ARM Inc themselves
448.
by phire 2y ago
It feels like the kind of optimization that gets missed because the task was split between multiple people, and nobody had complete knowledge of the problem. The person generating the table didn't realize filling the out-of-bounds with
449.
by phire 2y ago
Maybe.... Probably. Especially if I had left a detailed comment explaining why. But I still would have required an interim solution for everyone building from source until these patched/fixed versions of SDL started shipping in distros
450.
by phire 2y ago
I really don't know how much of the problem is me. For some reason, I have a really hard time groking Haskell, and Nix seems to fit in the same boat. I don't know why. It's not the functional programming. I love doing functio

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