obl

8 ms·

31.
Present Latency, DWM and Waitable Swapchains(jackmin.home.blog)
1 points by obl 5y ago|0 comments
32.
CppMem: Interactive C/C++ memory model(svr-pes20-cppmem.cl.cam.ac.uk)
3 points by obl 5y ago|0 comments
33.
The worst API ever made(caseymuratori.com)
5 points by obl 5y ago|0 comments
34.
Archetypal vs. Grouped ECS Architectures(community.amethyst.rs)
1 points by obl 6y ago|0 comments
35.
Why LuaJIT's interpreter is written in assembly(lua-users.org)
81 points by obl 6y ago|21 comments
36.
The Player Movement System in “The Witness”(caseymuratori.com)
3 points by obl 6y ago|4 comments
37.
Player Movement System for the Witness(youtube.com)
2 points by obl 6y ago|0 comments
38.
European Commission fines Valve and 5 publishers 8M€ for geo-blocking practices(ec.europa.eu)
1 points by obl 6y ago|0 comments
39.
Alibaba’s Ultra High-Performance RISC-V Superscalar Processor(embedded-computing.com)
2 points by obl 6y ago|0 comments
40.
Porting Detroit: Become Human from Playstation 4 to PC – Part 3(gpuopen.com)
1 points by obl 6y ago|0 comments
41.
ACO, a new compiler back end for GCN GPUs [pdf](xdc2019.x.org)
1 points by obl 6y ago|0 comments
42.
Clustered Forward vs. Deferred Shading(yosoygames.com.ar)
2 points by obl 6y ago|0 comments
43.
Clustered Forward vs. Deferred Shading(yosoygames.com.ar)
1 points by obl 6y ago|0 comments
44.
The Elusive Frame Timing(medium.com)
1 points by obl 6y ago|0 comments
45.
The Elusive Frame Timing(medium.com)
1 points by obl 6y ago|0 comments
46.
by obl 6y ago
If you're interested the dev had a cool GDC talk going over the design : https://www.youtube.com/watch?v=prXuyMCgbTc
47.
by obl 6y ago
That sounds very unlikely ? "The reason" why memory is slower than registers (apart from size obviously) is that register dependencies are static and can be easily tracked by the core. Memory is way harder since you don't kno
48.
A possible new back end for Rust(jason-williams.co.uk)
526 points by obl 6y ago|218 comments
49.
RISC-V Summit 2019: State of the Union(youtube.com)
6 points by obl 7y ago|0 comments
50.
HotChips 31: AMD Zen 2 microarchitecture(youtu.be)
1 points by obl 7y ago|0 comments
51.
How to design, build and test small liquid-fuel rocket engines(risacher.org)
1 points by obl 7y ago|0 comments
52.
LLVM RISC-V back end 'official' for 9.0(lists.llvm.org)
2 points by obl 7y ago|1 comments
53.
by obl 7y ago
Nice article. Of course if you get some of the benefits of run time specialization, you also get some of the downside, i.e., overspecialization. The heuristics to know when to stop specializing is a really hard part of those kind of systems
54.
Let’s Close the [DirectX 12] Buffer Zoo(joshbarczak.com)
1 points by obl 7y ago|0 comments
55.
PicoRV32 on an ASIC, Open-Source, Open Silicon(youtube.com)
2 points by obl 7y ago|0 comments
56.
Talks of the 2019 RISC-V Workshop(youtube.com)
3 points by obl 7y ago|0 comments
57.
by obl 7y ago
If I was more optimist, I'd say that this would be a good opportunity to open up silicon design by requiring some amount of transparency that is usually expected of publicly funded research. However I'm guessing that this initiati
58.
Qualcomm Invests in SiFive(electronicsweekly.com)
1 points by obl 7y ago|0 comments
59.
PowerVR GPU for RISC-V Available on SiFive Platform(design-reuse.com)
4 points by obl 7y ago|0 comments
60.
by obl 7y ago
Nice. I'm sure you could do a lot of cool things once you have this working well by playing around with the "butterfly effect". For example introduce a single X us jitter in the RTC interrupt and see how long it takes or whic

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