lgg

13 ms·

61.
by lgg 6y ago
Rob Enderle?
62.
by lgg 6y ago
You can do it in decode if the relevant operand is encoded as an immediate. I'm not aware of any processors that do any of the strength reductions discussed here in that way.
63.
by lgg 6y ago
I was not arguing the people writing code should perform strength reductions manually, I was explaining what they were and then stating that even ancient compilers do them automatically. While I did not explicitly state it, the logical foll
64.
by lgg 6y ago
Thanks for the heads up, unfortunately I got distracted with work, and I am no longer able to edit the post.
65.
by lgg 6y ago
It is not that the processor that contains an optimization per se. The thing to understand is that shift is fundamentally a simpler operation than multiply... a shift can be implemented with a few transistors per bit and done in a single cy
66.
by lgg 7y ago
I'll provide a specific issue I had, which is that the charts don't provide good units or labels. For example, on the Week by Week breakdown chart the vertical axis is labeled "Duration" and and has bars that range from
67.
by lgg 7y ago
When the first 64 bit Macs shipped none of the software was 64 bit clean. Even if the kernel source code had been 64 bit clean, it would have broken support for all the the 3rd party 32 bit drivers that existed. So the kernel switched itsel
68.
by lgg 7y ago
We have no idea if it was even undefined in the first place, since the PPU documentation is not public. You are correct thought, often guarantees about behavior can be made after the fact. Generally what happens these days is someone determ
69.
by lgg 7y ago
When you install a mach exception handler you can get the port of the previous exception handler, which you can use to forward the messages your newly installed exception handler receives. Of course (as with all raw mach APIs) it is poorly
70.
by lgg 8y ago
I completely agree. I was just responding that linking is intimately related to the ISA, which is relevant since the FowardCom info states that it does not support dynamic linking and instead all objects are instead relinkable (in the same
71.
by lgg 8y ago
Linking is always a largely a function of the ISA, because it is about taking partially finished chunks of code and glueing them together. In the case of dynamic libraries part of that has to do with the OS, more of it has to do with the in
72.
by lgg 8y ago
Most modern architectures make extensive use of PC-relstive instructions for branches and load/store. That means when rebasing a binary you just need to modify the pointers in the data segment (things like GOT entries, etc) and can lea
73.
by lgg 8y ago
Interesting article, but I have one nit. I don't think your reasoning behind why Objective C does not support overloading is sound. Selectors are completely incompatible with C function names anyway. For example, they are only relevant
74.
by lgg 9y ago
Thanks for the heads up. It should be taken care of now.
75.
by lgg 9y ago
The link you posted has nothing to do with how GCC does codegen. It is about GCC transitioning itself from being written in C to being written in C++.
76.
by lgg 9y ago
It is not about recording the interactions, it is about processing the content. Every time a doctor has to interact with a computer it is time they are not interacting with their patient. Augmedix has teams of medical scribes who watch the
77.
by lgg 9y ago
No, it is actually (mostly) correct. In ST:TNG they redefined the definition such that it is infinite. It was documented in the Star Trek: The Next Generation Technical Manual , which was published in 1991 and was written by the technical
78.
by lgg 9y ago
It depends on the platforms C ABI, but no, the argument marshaling for va_args is not necessarily (or even usually) the same as normal args. In the case of iOS you can look here[1], the relevant bit being: "The iOS ABI for functions th
79.
by lgg 9y ago
It actually is not the extra function call that is the big hit, since if you think about it objc_msgSend also does two calls (the call to msgSend, which at the end then tail calls the imp). The dynamic instruction count is also roughly the
80.
by lgg 11y ago
SF does not have an income tax. It does have a 1.5% payroll tax that is paid by employers, but that is already factored into your your gross pay (IOW, if a company offers you 90k the pay the $1,350 in taxes and you never deal with it). You
81.
by lgg 11y ago
I am sure the author is correct the dies are the same, but it is not particularly evil or genius, it is just making you pay for costs associated with software they included. Effectively they are charging different amount for different softw
82.
by lgg 11y ago
True, I should have said it is not concurrently stopping all the threads. If you actually need the register state of a thread that is currently running on another processor it may be stopped to get it (though if you ask for the state of a t
83.
by lgg 11y ago
Totally platform specific. On OS X you generally use thread_get_state().
84.
by lgg 11y ago
Yes, obviously you may need barriers or fences depending on the exact architectural details, and as another commenter mentioned you may be able to elide the read barrier if you know what is going on. This all about optimizing things so the
85.
by lgg 11y ago
It isn't actually stopping the threads. The thing to understand is that you don't need to ensure that all threads are outside of a critical section at the time you free the cache, what you need is the weaker guarantee that all thr
86.
by lgg 11y ago
HFS+ stores the extent records for certain essential files (the bootloader, the catalog file, the extents overflow file, the journal, etc) in the file system header. So in order to find their physical locations you just need to read in the
87.
by lgg 12y ago
It has almost no one effect on L1/L2 cache usage. CPU caches tend to work on 64-128 byte cache lines. Most of the lines in s mostly zero page will never get touched so they will never enter the cache.
88.
by lgg 12y ago
This is system C the memory is manually managed with malloc(). You can't simply nil the reference and expect GC to come through and clean it for you, you have to issue a free() for each malloc() that was called. While it might be possi
89.
by lgg 12y ago
Well sure, different implementations behave differently. It still has nothing to do with being OoOE... A 486 and an original Atom are both in order implementations the i386 architecture (though both also implement other extensions), but kno
90.
by lgg 12y ago
Out of order processors do not "kill" determinism. If you can guarantee your initial state is the same you will get the same result in the same number of cycles repeatably. The fact that time it takes is non-obvious does not make

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