janwas

28 ms·

391.
by janwas 4y ago
hm, I have had limited success with such nudging - it's certainly not a programming model with a predictable outcome. And as soon as the compiler or its flags are updated, maybe the situation changes.
392.
by janwas 4y ago
> the much bigger problem with SIMD is that it is really hard to program for since vector sizes keep getting bigger This can be fixed with an abstraction layer such as github.com/google/highway (disclosure: I am the main author
393.
by janwas 4y ago
I've seen 1.5-1.6x speedups in an image codec, and Quicksort - despite any frequency reduction. As others are saying, it really is a nicer and much more complete instruction set than AVX2.
394.
by janwas 4y ago
I believe they do actually do something like this - until power and voltage delivery change, wide instructions are throttled independently of frequency changes (which on SKX involved a short halt).
395.
by janwas 4y ago
I would love to see an example of reasonable code not seeing any benefit. On first generation SKX, we saw 1.5x speedups vs AVX2, and that was IIRC even without taking much advantage of AVX3-only instructions.
396.
by janwas 4y ago
Fair point about ifunc, but we're using our own table of function pointers, which can be invalidated/re-initialized. Someone also mentioned that the OS could catch SIGILL.. indeed seems doable to then reset thread affinity to the
397.
by janwas 4y ago
:) I have actually heard it referred to as AVX3, we also adopted that name in Highway.
398.
by janwas 4y ago
One interesting anecdote is that HPC planning for exascale included significant concern about machine failures and (silent) data corruption. When running at large enough scale, even seemingly small failure rates translate into "oh, the
399.
by janwas 4y ago
My point is that vector instructions are fundamentally necessary and thus "what does it signal" evaluates to "nothing surprising". Sure, REP STOSB/MOVSB make for a very compact memset/memcpy, but their performa
400.
by janwas 4y ago
Why is a large speedup from vectors surprising? Considering that the energy required for scheduling/dispatching an instruction on OoO cores dwarfs that of the actual operation (add/mul etc), amortizing over multiple elements (=SIM
401.
by janwas 4y ago
I agree it makes sense to group the many x86 features into just 3-4 clusters, though Intel probably uses more. Makes sense that BLAS has many other variations. Still, hard to see why that necessitates gigabytes :)
402.
by janwas 4y ago
I don't understand why the multiple versions are a major concern? We shipped 3 codepaths for JPEG XL (SSE4/AVX2/AVX-512) with a binary size of a few hundred KiB. that's ~10 KLOC, and ~5-7 bytes per x86 vector instruction
403.
by janwas 5y ago
Thanks for the example! Sounds like 1.6 GB/s on an entire Tesla K80 (300W TDP). This is in fact several times slower than our results on Skylake (with half the TDP), but note that K80 is from 2014. The "25-fold speedup", as i
404.
by janwas 5y ago
Golly, another sweeping statement :) It seems to me a GPU might actually sort more slowly. For 64-bit keys, we sort about 1 GB/s per (5 year old) Skylake core, and perhaps 5-6 parallel. This (2018) reports 3.5 GB/s: https:/&
405.
by janwas 5y ago
That's a bold claim. What are your sources? The two latest things I worked on, JPEG XL and quicksort, see a 1.4 and 1.6x speedup from AVX-512. That's on SKX and includes the much-maligned throttling. On a system level, I doubt mov
406.
by janwas 5y ago
Oh, you are using Phi :) My viewpoint is likewise biased towards desktop and server systems. Fair point about heterogeneous cores. I suspect those aren't going away. Perhaps the industry should move to a model where threads are tempora
407.
by janwas 5y ago
:) I'm curious what makes it not worthwhile? From my point of view it's just an additional compilation pass of your SIMD kernels (written using github.com/highway; disclosure: I am the main author), plus shipping a few tens&#
408.
by janwas 5y ago
Not sure why the AVX-512 situation is complicated. As paulmd commented, in practice all the various avx512* supported by more recent chips (except Phi) are supersets of the previous ones. github.com/highway compiles the same source cod
409.
by janwas 5y ago
Those are surprising claims. Browsers and their video/image codecs use SIMD. Other usages in office/productivity apps include Photoshop/Lightroom, video editing, compression, CAD.
410.
by janwas 5y ago
It's indeed nice that SVE2 binaries can run on differing HW, and fragmentation will be less because it's required in ARMv9. > the same code will work for both the super-computer and the cheap phone. That is not possible with th
411.
by janwas 5y ago
Yes, our github.com/google/highway does that for SSE4/AVX2/AVX-512. It targets at the level of instruction sets, though, not specific microarchitectures.
412.
by janwas 5y ago
+1, I use it in front of a Maltron L90 keyboard, plus a trackball on the side.
413.
by janwas 5y ago
Indeed, degree-4 rational polynomials are generally enough for JPEG XL. Code for evaluating them using Horner's scheme (just FMAs): https://github.com/libjxl/libjxl/blob/bdde644b94c125a15e532b... I initi
414.
by janwas 5y ago
Thanks for sharing the examples! Looks like broadcast and replicating one element, which works if we know there are only 4 elements. > I was doing something like that, saving a few instructions Oh, nice one. > I think ARM is good enou
415.
by janwas 5y ago
:) The benchmark does contain some boilerplate and extra code for measurements but a simple example is at https://github.com/google/highway/blob/master/hwy/examples/b... . Or how about https:&#
416.
by janwas 5y ago
Thanks for posting :) Author here, happy to discuss.
417.
by janwas 5y ago
> _mm256_blend_pd is very fast instruction, a single cycle of latency. The highway’s emulation is going to be way more expensive. Actually it uses exactly the same instruction :) https://github.com/google/highway&#x2
418.
by janwas 5y ago
> things like that (highway, OpenMP 4.0+, automatic vectorizers) are only good for vertical operations. I agree autovec and #pragma omp simd struggle with any kind of shuffles, but Highway does not belong in that category - it offers mor
419.
by janwas 5y ago
Totally agree software uptake is the pain point. Not even all gamer CPUs have SSE4 ( https://store.steampowered.com/hwsurvey ), so it seems that runtime dispatch is unavoidable. Given that, if we can afford to generate code f
420.
by janwas 5y ago
> In my line of work, AVX512 is useless. This won't change until at least 25% market penetration on clients, which may or may not happen. Why not use it where available? github.com/google/highway lets you write code once u

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