igodard

8 ms·

1. 61.▲
   by igodard 13y ago

   Re Scheduling for latency: Decades-old compiler tech can produce near-perfect schedules for in-order machines (including VLIWs) for all operations with a statically-fixed latency, which in practice means everything but loads. A load miss wi
2. 62.▲
   by igodard 13y ago

   In terms of square millimeters the caches dominate chip area. In terms of fab yield (which is the cost driver) they do not, because caches are regular structures that are built with built-in sparing. If there's a bad gate in the cache
3. 63.▲
   by igodard 13y ago

   The Mill compiler is a conventional three-phase tool. The first version used the EDG front end and home-grown middle and back ends, but we are converting to a clang front end, LLVM middle, and home-grown back end. All optimization is done i
4. 64.▲
   by igodard 13y ago

   I'll try to address some of the questions and issues raised here; the Mill has been more fully discussed on comp.arch, and there is more material at ootbcomp.com/docs. Sign up at ootbcomp.com/mailing-list to get announcements