dzaima

48 ms·

511.
by dzaima 2y ago
What introduced UB are you thinking of? I'll admit I don't know how much has changed, but the usually-complained-about things (signed overflow, null pointer dereferencing, strict aliasing) are clearly listed as UB in some C89 draf
512.
by dzaima 2y ago
The vast majority of UB usually considered problematic has been in the standards for decades, long before compilers took as much advantage of it as they do now (and the reasons for including said UB back then were actual hardware difference
513.
by dzaima 2y ago
> Except that compiler writers essentially decide what's UB. No, the C/C++ standards specify what is UB. So, as long as you don't switch targeted standard versions, the brokenness of your code never changes. Compilers may
514.
by dzaima 2y ago
On the Python example, the downside is that, even though the order is unspecified, people may still rely on some properties, and have their code break when an optimizer changes the order. Basically the same as UB really, though potentially
515.
by dzaima 2y ago
Zen 4 has two 32-entry schedulers for SIMD, which I think is the relevant buffer here (many of my numbers in this thread, including these, are coming from https://chipsandcheese.com/2022/11/05/amds-zen-4-part-
516.
by dzaima 2y ago
Assembly is a good fallback, but it requires that individual programmers special-case individual architectures (thus each likely ending up with an incomplete list, and definitely incomplete as soon as it stops being updated) instead of havi
517.
by dzaima 2y ago
AMD64 manual volume 4 ( https://www.amd.com/content/dam/amd/en/documents/processor-t... ): > Exception and trap behavior for elements not selected for loading or storing from/to memory is impl
518.
by dzaima 2y ago
Indeed, if you an want immediate error on every out-of-bounds read, this won't be suitable. I do think one should always have the option to not opt into this. But there still exist use-cases where the benefit of being able to do partia
519.
by dzaima 2y ago
This is what I do too (in my case I don't round up the allocation size and just let loads & stores potentially see the next object (doing tail stores via load+blend+store where needed; only works if multithreaded heap mutation isn&
520.
by dzaima 2y ago
Worse yet (for wiring complexity or required uops, anyway), AVX-512 also has shuffles with two data inputs, i.e. each of the 64 bytes of result can come from any of 128 different input bytes, selected by another 64-byte register.
521.
by dzaima 2y ago
Sorry, mixed things up - store has a limit of one 32-byte store per cycle (load is what has two 32-byte/cycle). Of additional note is Zen 4's tiny store queue of 64 32-byte entries, which could be at play (esp. with it pointing at
522.
by dzaima 2y ago
On clang masked load/store tail - there are some flags to change its behavior, but seems like nothing does just a masked tail, and what does exist still has work to do, e.g. here's a magic incantation that I found looking through
523.
by dzaima 2y ago
The store will still take up throughput even if nothing depends on it right now - there is limited hardware available for copying data from the register file to the cache, and its limit is two 32-byte stores per cycle, which you'll hav
524.
by dzaima 2y ago
It should still be with "UB only if the hardware doesn't like it", of course. If weird funky hardware not following usual memory paging is of worry, providing a "memory_protection_granularity" constant is trivial, t
525.
by dzaima 2y ago
Also of concern is that the input, and thus the loads & stores here, are intentionally bumped to cycle through all possible alignments, thus ending up unaligned most of the time, in which case it should be 3 cycles per store (I think?).
526.
by dzaima 2y ago
Masking is nice, but not available everywhere (i.e. intel is still making new generations of CPUs without AVX-512, and apple silicon doesn't have any masked loads/stores either). It might not be the nicest thing to assume to be th
527.
by dzaima 2y ago
Here it'd be perfectly fine to define it as "completely arbitrary bits past the end, potentially even differing between back-to-back calls of loading the same memory"; specific backends will end up refining that of course. In
528.
by dzaima 2y ago
This shouldn't ever be a security vulnerability, outside of perhaps denial of service from segfaults (though I'm pretty sure you'd find hardware with no page faults before finding one with pages less than 4KB; and of course,
529.
by dzaima 2y ago
It would be neat to have non-assembly options for things like this. A "load with unspecified elements for any values past the end of the allocation, UB only if the hardware doesn't like it" thing shouldn't be hard to sup
530.
by dzaima 2y ago
Unrolling on AVX-512, especially on Zen 4 with its double-pumped almost-everything, isn't particularly significant; the 512-bit store alone has a reciprocal throughput of 2 cycles/zmm, which gives a pretty comfortable best possibl
531.
by dzaima 2y ago
RVV has: masking for everything (though for things like loop tail handling (or even main body) using VL is better and much nicer); all the usual int & FP widths; indexed (gather & scatter) & strided & segmented loads & s
532.
by dzaima 2y ago
RISC-V does have RVV, which similarly can do SIMD, has masking, but also has a vector length separate from masks: https://godbolt.org/z/rrEW85snh . Complete with its own set of ~40000 C intrinsics ( https://dz
533.
by dzaima 2y ago
I was indeed using 'a properly implemented one' for a non-microcoded implementation there.
534.
by dzaima 2y ago
"implemented in microcode at first" has massive downsides if the microcode isn't particularly fast. e.g. AMD Zen 1 and Zen 2 support BMI2 and thus pdep & pext, but they're microcoded, so up to hundreds of times slowe
535.
by dzaima 2y ago
That's an interesting solution. Would also not be unreasonable for like indexed loads/stores, though there fully getting rid of the built-into-instruction element type would have its problems. While vrgatherei32 is certainly defin
536.
by dzaima 2y ago
If what camel-cdr in another comment here said is correct, the single-cycle vrgather wouldn't apply to anything not written specifically for X280 as I doubt anything anywhere is attempting to use LMUL=1/2 for 128-bit or 256-bit vr
537.
by dzaima 2y ago
It's only not worth it if software indeed consistently does the LMUL=1 unrolling. Which I suppose most will, and vrgather with LMUL>1 will be roughly dead-on-arrival, but who knows.
538.
by dzaima 2y ago
That is exactly my design (or, rather, a design I remember reading in the #riscv IRC room), taking the "could also have only one DLEN-sized table chunk input at the obvious cost" path; i.e. to extend your specification to my doubl
539.
by dzaima 2y ago
There is the better, but much more complex, option of a variable-latency vrgather, where, for each DLEN-sized output segment, it counts the number of distinct DLEN-sized chunks of the table the current indices require, and spends, say, ceil
540.
by dzaima 2y ago
More precisely, rr records just system calls & interrupts, so its overhead is largely proportional to how syscall-heavy and multithreaded your code is. If it's single-threaded and mostly just pure computation, you can easily see ~0

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