drob518

34 ms·

931.
by drob518 1y ago
The only non-arbitrary boundary is the one set by physics. Everything else is arbitrary. There are ways to greatly reduce front-running of orders, but that actually is an orthogonal issue to HFT and microstructure level trading.
932.
by drob518 1y ago
Right. “Worth” and “price” are relative notions that are only useful when paired with a point of view. What’s your house “worth?” You might have a number in your head, but unless you have a buyer willing to transact at that price, your hous
933.
by drob518 1y ago
So, seconds good but milliseconds bad? That seems rather arbitrary.
934.
by drob518 1y ago
Do you only want us to get our news once daily via a physically printed and distributed newspaper? That’s the timeframe that we used to use for news updates. If not (I.e., you’re in favor of keeping the Internet), how would you reconcile th
935.
by drob518 1y ago
I suspect that randomness of some sort is the only way. Without that, whatever the rules of the game, there is a way to somehow get a slim advantage. You can make the advantage small and the costs to try to gain it large, such that it isn’t
936.
by drob518 1y ago
So, you want everyone to trade only daily or weekly or quarterly?
937.
by drob518 1y ago
Seemed like a red herring. They were able to reproduce it without any libraries. Might have just been net link forcing the stacks to a certain size and that made the bug visible.
938.
by drob518 1y ago
Exactly what ran through my mind.
939.
by drob518 1y ago
That’s the right answer, IMO. To me, that sounds a lot like a RISC with some complex instructions, which is really where all RISCs have landed in any case. That said, I would use fixed length compressed instructions ala Thumb and RISC-V Com
940.
by drob518 1y ago
I agree that cache efficiency is important. You can never have enough L1. It seems to me that compressed instructions ala ARM Thumb and RISC-V Compressed give you most of what you really want. One of the problems in the CISC era was that th
941.
by drob518 1y ago
Hm. Maybe I’m using terms incorrectly or my model for what is happening is incorrect. Please educate me. “NOT a load/store architecture.” What do you mean by this, exactly? “It's a simpler version of the external ISA, NOT a RISC.”
942.
by drob518 1y ago
Yep, I agree. Your eyes need these clues to help you read at speed. When every character looks similar, you have to slow down to look at individual characters, rather than just glancing at a whole word.
943.
by drob518 1y ago
OK, fair enough that one doesn’t necessarily imply the other, but if you were designing a CPU/ISA today, would you start with a CISC design? If so, why?
944.
by drob518 1y ago
Can’t fault his logic.
945.
by drob518 1y ago
Yep. I think by the time the web arrived, it was pretty common for the windowing systems (e.g., Windows, Mac System whatever, OpenVue, Next, etc.) to have black text on white backgrounds to mimic paper output.
946.
by drob518 1y ago
I suspect it’s for the same reason that the two most popular pen colors are black and blue. On light backgrounds, blue shows up well and doesn’t impede readability. So, if all your text is black by default and you want another default color
947.
by drob518 1y ago
Sure, it’s not coded the same way as your external ISA does it (like you said, lots of wide information), but the core is optimized for a load/store architecture with ops that generally execute in a single pipeline stage, and the big,
948.
by drob518 1y ago
I wonder how many airplanes are going to fall out of the sky? Or maybe we have to wait until January 1, 10000, for that.
949.
by drob518 1y ago
Exactly. I mean, if the end solution is to convert to a big int, who’s to say that some customer didn’t assume it would always be 32 bits and blow up then, too. This does highlight the fact that 32 bit is just a small number these days. Per
950.
by drob518 1y ago
Sure, they’re getting less free and they were never completely free in any case. But that’s a straw man that nobody was trying to argue. So (again), what’s your point?
951.
by drob518 1y ago
What point are you trying to argue with everyone? You seem to be quibbling over everything without stating an actual POV.
952.
by drob518 1y ago
Amen. The syntax just kept getting more and more complicated. I gave up in the late 1990s. Ironically for this post, I now prefer to write everything in Clojure. It seems like my own journey has paralleled Rich’s journey. Maybe that’s why I
953.
by drob518 1y ago
I’m not sure what point you’re trying to get me to concede. I’ve already stated that I’m on the RISC side of the debate. If your point is that it’s difficult to keep doing this with x86, I won’t argue with you. But that said, the x86 teams
954.
by drob518 1y ago
Most architectures never actually die. New architectures just snap up the balance of the new designs. That said, a competitive license-free ISA is quite attractive to a lot of people, and once the snowball gets moving it will grow in size a
955.
by drob518 1y ago
Yes, that’s why I said almost free. But that said, as I understand it, the x86 decoders aren’t that much of the die area of a modern design. Most of it is L1 cache, GPUs, neural engines, etc., which makes simple die area comparisons of mode
956.
by drob518 1y ago
I think you’re just making my point.
957.
by drob518 1y ago
Well, you would be foolish to design the x86 now if you had a choice in the matter. Zen5 is a RISC at heart, with a really sophisticated decoder wrapped around it. Nobody uses x86 or keeps it moving forward because it’s the best instruction
958.
by drob518 1y ago
I’m not sure I get your point? Are you saying it is impossible to accelerate the VAX instruction set via the same technique used on x86? If so, you’ll have to explain why. Now, whether you’d want to or not is another question.
959.
by drob518 1y ago
I’m talking about a VAX-like system with large instructions, microcode-based, etc. In the same way that CISC adapted since 1990, RISC has also adapted to add “complex” instructions where they are justified (e.g. SIMD/vector, crypto, ha
960.
by drob518 1y ago
Exactly. If you’re going to design a new ISA, you’d be foolish to make it a classical CISC design and would definitely choose RISC (e.g., RISC-V). But if you have a CISC ISA and you want to keep it running fast, then a virtually unlimited t

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