dist1ll

10 ms·

91.
by dist1ll 3y ago
Per-core store bandwidth is at least 14GB/s on Zen3, 35GB/s for non-temporal stores. Parsing JSON can be done at +2GB/s. It's very healthy to take maximum bandwidth limits into consideration when reasoning about performa
92.
by dist1ll 3y ago
I have a feeling many of the common multithreading optimizations carry the same flaw as incremental compilation: they give you good speed-ups in the short term, but potentially mask deeply flawed architectural decisions. Essentially improvi
93.
by dist1ll 3y ago
No, just ordinary distributed systems stuff. tokio, serde, bincode, error/logging/testing crates, and stdlib.
94.
by dist1ll 3y ago
> in practice with many Rust programs that iteration cycle is actually not "edit, compile, run", it's "edit, save, wait for rust-analyzer to update" which is generally much quicker Rust-analyzer is struggling sig
95.
by dist1ll 3y ago
Unfortunately that means the chunks are only contiguous in virtual memory. So it won't work with the DMA use case mentioned in the article, which requires contiguous physical addresses. But it's still a nice trick, I like it when
96.
by dist1ll 3y ago
It's really not much work, and it removes another source of dependency/build bloat. Also, if you care about speed, hand-rolling your lexer will always be the fastest (and even naive implementations can rival/outcompete genera
97.
by dist1ll 3y ago
I suspect that lexer generators mostly exist because that's what people who want to implement compilers are being taught. But there's nothing difficult about writing a lexer. It can be done in less than 100 LoC, easily half that i
98.
by dist1ll 3y ago
Cool article. I think what the author calls "sheep race" is known as loop rotation. This allows you to mask off latency, at the cost of wasted computation at the tail of the loop.
99.
by dist1ll 3y ago
> “We want to open [Metalium] to the point that everything is 100% transparent,” she said. “We will click ‘open’ on our Github repo, and the world will be able to see everything that we’re doing internally. That's would be massive.
100.
by dist1ll 3y ago
Last time me and a coworker tried out Zellij (a few weeks ago), there was noticeable input lag compared to tmux. Used the most recent macOS release, running in alacritty w/ zsh. Anyone else had an experience like that? I think for term
101.
by dist1ll 3y ago
I'm currently taking the same route with my compiler. It's written with extreme efficiency in mind, so I'm planning to expose a client-side WASM binary on the main site, that will let you interactively explore the language wi
102.
by dist1ll 3y ago
> it's now actually very fast at compiling small incremental changes in debug mode. This breaks down quickly at scale. If you reach significant code complexity, even with dedicated build machines, remote Bazel builds & distribu
103.
by dist1ll 3y ago
> one really great feature of Wirth's Pascal is nested functions with access to outer scopes, which D wholeheartedly embraces Can you give an example? What does the function access in the outer scope? Is it like an environment-captu
104.
Every 7.8μs your computer's memory has a hiccup(blog.cloudflare.com)
12 points by dist1ll 3y ago|0 comments
105.
by dist1ll 3y ago
> I think this approach can operate at RAM speed with just one core with AVX512, so no benefit in splitting across cores. A single core can't saturate RAM bandwidth. Cores are limited by memory parallelism and latency. Most modern x
106.
by dist1ll 3y ago
Thanks for the thoughtful comment, pretty fascinating stuff. > In today's x86_64 hardware, there's no "supercomputer memory subsystem". It's just a glorified NUMA system, and the biggest problem is putting the me
107.
by dist1ll 3y ago
It's very interesting how abtracted away HPC sometimes looks from hardware. The books seem to revolve a lot around SPMD programming, algo & DS, task parallelism, synchronization etc, but very little about computer architecture deta
108.
by dist1ll 3y ago
Very likely the majority of the file is paged in, and can be prefetched just fine. The author doesn't clear/disable the page cache.
109.
by dist1ll 3y ago
> Perhaps something like 'the branch for input x is somewhere around base+10X. That's unlikely. Branch predictors are essentially hash tables that track statistics per branch. Since every branch is unique and only evaluated onc
110.
Modern Microprocessors – A 90-Minute Guide(lighterra.com)
2 points by dist1ll 3y ago|0 comments
111.
Performance Speed Limits(travisdowns.github.io)
2 points by dist1ll 3y ago|0 comments
112.
So You Want to Optimize Your Code?(yoric.github.io)
2 points by dist1ll 3y ago|0 comments
113.
by dist1ll 3y ago
IPC is not a good performance metric - especially for an instruction set like x86, but particularly for SIMD ISAs. Two seemingly similar instructions sequences may get decoded into a different number of uops, which in turn occupy different
114.
by dist1ll 3y ago
ISPC https://ispc.github.io/
115.
Recognizing string prefixes with SIMD instructions(lemire.me)
4 points by dist1ll 3y ago|0 comments
116.
by dist1ll 3y ago
How often do you need highly optimized cg during development? Unless I'm working on games, 99.9% of my time (even on highly performance-critical software) is spent on evaluating debug builds with 0 perf requirements - because I need to
117.
by dist1ll 3y ago
All of this is fascinating. I believe single-pass compilation is underrated, and quickly disregarded by a large body of the PL community as anachronistic. I think that's complete nonsense. Just take one look at the massive build infras
118.
by dist1ll 3y ago
Being more ergonomic than C++ is a low bar anyways, we should hold ourselves to a higher standard. For starters, field offset syntax is painful (see Gankra's post on this topic) and pointer manipulation lacks syntactic sugar. I also be
119.
by dist1ll 3y ago
Great article, and it’s pretty interesting to see portable simd in use. I tried reproducing the benchmarks on a Zen 3 system, and I’m getting identical speedups. On my M1 mbp, the perf gains start around 1.4x, gradually increasing to 2x @ 1
120.
by dist1ll 3y ago
Replacing hardware? Sure, they'll help. What about debugging firmware though? I'm curious how much help you would get from Dell fixing and patching complicated firmware errors. A side benefit of the openness is that firmware issue

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