deadgrey19

19 ms·

121.
by deadgrey19 12y ago
Thanks. I guess I'm trying to give some sort of indication that I know what I'm talking about. Too many people have opinions without any factual basis to make them on. I'll try to be more toned down in the future.
122.
by deadgrey19 12y ago
It's not just you. If you read it carefully you'll notice that the evaluation only shows that the improvements are that TCP retransmits are reduced from 4 to 2 per second, which probably has no impact. And that the latency is only
123.
by deadgrey19 12y ago
Dubious. The question is what the tail response time of the arbiter is at full load. The key measurement (which is conspicuously absent from the paper) is the impact on the end-to-end delay at varying load. A distribution graph of this woul
124.
by deadgrey19 12y ago
As context, I am a researcher in datacenter networks at a world renowned university. I've read the full research paper in detail, several times (not just the media summary) and have reviewed it carefully with other researchers in this
125.
by deadgrey19 12y ago
This is fantastic, if you want to solve only maths problems. But when there is real state and real side-effects and real hardware matters, this sort of approach breaks down.
126.
by deadgrey19 12y ago
On of the serious drawbacks of Netmap is that it amortizes, but does not mitigate system call latencies. This means that although it can handle high packet rates, latencies for processing are dominated by the system call overhead (typically
127.
by deadgrey19 12y ago
Typical capture cards have a resolution of 6-7ns. 300ns PHY is an out of date value. These guys can do ~425ns wire to application (or 850ns round trip to software) http://exablaze.com/exanic-x4
128.
by deadgrey19 12y ago
This stack may be open source, but it is handcrafted to work only with the Solarflare NICs. Having looked at it seriously, we decided that it wasn't worth trying to port this to our own devices and therefore wrote yet another one. This
129.
by deadgrey19 12y ago
There are one or two. The most prominent is Netmap ( https://code.google.com/p/netmap/ ) another is the Intel Dataplane Development Kit (DPDK - http://www.dpdk.org/ . Both of these allow you to handl
130.
by deadgrey19 12y ago
I'm not an OCaml programmer, so much of this document goes over my head, but I have done a lot of thought about multi-core and multi-thread processing. It seems to me (and this is along the lines of your document, if I'm reading i
131.
by deadgrey19 12y ago
Finally! Microsoft has realised that real developers use OS X/Linux for development and don't have or care to test on Windows machines. This is a good thing for Microsoft and a good thing for the web!
132.
by deadgrey19 12y ago
I can't answer all of these questions authoritatively, as I have more of a systems focus than a formal methods focus, but I can hopefully point you in the right directions. The various published papers and final release will be the rig
133.
by deadgrey19 12y ago
To be fair. Every operating system assumes these things. At least the seL4 team has made this explicit. Secondly, there is a tiny amount of this code amounting to a few hundred lines of assembly and there are numerous verified hardware proj
134.
by deadgrey19 12y ago
Source: I have worked at NICTA, with the seL4 team, on the seL4 project, I've seen the seL4 source code and am (was?) a primary author of the user manual. These claims have been peer reviewed in top formal methods and operating systems
135.
by deadgrey19 12y ago
Beware, since the source is a translation of Haskell into C, this is not an entry level source tree and is not straightforward to read/understand despite it's small (LOC) size.
136.
by deadgrey19 12y ago
Source: I have worked at NICTA, with the seL4 team, on the seL4 project, I've seen the seL4 source code and am (was?) a primary author of the user manual. What they mean by this is that they have specified certain properties at a high
137.
by deadgrey19 12y ago
Verilog and VHDL are equivalent in the power of expressiveness, one is more or less interchangeable with the other. Both are supported by both major chip vendors (Xilinx and Altera). Although neither vendor supports anywhere near the latest
138.
by deadgrey19 12y ago
And, according to the research paper ( http://research.microsoft.com/pubs/212001/Catapult_ISCA_2014... ) the benefits aren't especially convincing. - 95% throughput increase at same tail latency, - 29% tail la
139.
by deadgrey19 12y ago
It didn't work very well, but there is a good reason: Nobody wanted a slow and comparatively low performance chip paired with a small FPGA connected via a (slow) PCI-express connect. There are hundreds of big FPGA boards with PCIe conn
140.
by deadgrey19 12y ago
Unlikely. Custom built Application Specific Integrated Circuits (ASICs) (i.e. bitcoin mining chips - e.g http://www.butterflylabs.com/ ) will always be faster than FPGAs (which are comparatively slow) and CPUs (which are fas
141.
by deadgrey19 12y ago
My experience ( http://www.cl.cam.ac.uk/research/security/ctsrd/cheri.html , http://netfpga.org/10G_specs.html ) is that both of the toolchains are terrible on both of the platforms. Xilinx and
142.
by deadgrey19 12y ago
The first thing to know is that Verilog is not a programming language. It is a hardware description language. This may sound picky, but it fundamentally changes the way you need to think about using the language. With Verilog/VHDL&#x2F