corsix

8 ms·

31.
by corsix 4y ago
Given latency 3 / throughput 1, the only reasonable implementations are: A) Three ports, each non-pipelined, taking 3 cycles B) One port, with three-cycle pipeline (each cycle, one instruction can enter the start of the pipeline, and a
32.
by corsix 4y ago
https://uops.info/html-instr/CRC32_R64_R64.html answers that for you. Zen2 and Zen3 same as Intel: latency 3, throughput 1. Older AMD chips less good.
33.
by corsix 4y ago
The math is fiddly to get right, but (as the author) I'd suggest that the disadvantage is very tight coupling to the CPU implementation: the interleaving is based on the relative speeds of the two methodologies, so if the relative spee
34.
Seeing the Raft for the Trees(corsix.org)
2 points by corsix 4y ago|0 comments
35.
Reed-Solomon for Software Raid(corsix.org)
3 points by corsix 5y ago|0 comments
36.
by corsix 6y ago
There's good evidence for mask registers and x87 registers sharing the same hardware on recent Intel chips: https://travisdowns.github.io/blog/2020/05/26/kreg2.html
37.
by corsix 6y ago
An Intel Haswell chip, when doing floating point vector operations, can dispatch one addition per cycle, or two fused-multiply-add. The latency is worse for the FMA (5 cycles versus 3 cycles), but if you've got enough parallel accumula
38.
by corsix 9y ago
Concretely, https://twitter.com/corsix/status/948670437432659970 can be used to get both `movzx rax, byte [somekerneladdress]` and `movzx rax, byte [rax+someusermodeaddress]` executed speculatively (the idea behin
39.
by corsix 9y ago
Implementations of meltdown do not need to trigger a page fault (because the instruction which would fault can be made to execute speculatively - in addition to the instruction which leaks information into the cache executing speculatively)
40.
by corsix 9y ago
Only if __STDC_IEC_559__ is defined, which implementations are not required to do (in C++, the equivalent is std::numeric_limits<float>::is_iec559).
41.
by corsix 9y ago
The end of the post alludes to part 2 ("how to adapt nd_print into something which can behave like the %e, %f, and %g formats of sprintf"), which alas I've yet to get around to writing. There'll also be at least one more
42.
by corsix 9y ago
The solution is included in 2.1.0-beta3: "LuaJIT for x64 can optionally be built for LJ_GC64 mode by enabling the -DLUAJIT_ENABLE_GC64 line in src/Makefile or via 'msvcbuild.bat gc64'." "This mode removes the 3
43.
by corsix 9y ago
The commit author doesn't tell the whole story: the long description on most of the recent commits mention somebody else.
44.
by corsix 10y ago
IDA certainly complains a lot when it sees this.
45.
by corsix 10y ago
Thanks for the hug of death - I've turned on more aggressive CloudFlare caching.
46.
Estimating pi with LuaJIT(corsix.org)
6 points by corsix 10y ago|0 comments
47.
by corsix 10y ago
They've explored that route - and at least in my case, I so almost very nearly accepted their offer.
48.
by corsix 10y ago
Try building (the `v2.1` branch of) LuaJIT with `CFLAGS=-DLUAJIT_ENABLE_GC64`. This flag is a relatively recent addition [1], and didn't have JIT support on x64 until really very recently [2], but it should free you from the 4gb limita
49.
by corsix 10y ago
Finding someone who is competent, willing, and available is remarkably difficult.
50.
by corsix 10y ago
Or patch the export table of the exporting DLL in addition to the import table of every current importing DLL (as future importing DLLs will look in the export table).
51.
by corsix 10y ago
For reference, this has been fixed in LuaJIT master (with an instruction length decoder).
52.
Malicious LuaJIT bytecode(corsix.org)
4 points by corsix 11y ago|0 comments
53.
by corsix 11y ago
I am very pleased to see people building upon my Lua bytecode research, and I wouldn't be surprised to see more applications with embedded Lua which are exploitable like this.
54.
GCC target confusion(corsix.org)
2 points by corsix 12y ago|0 comments