cfallin

54 ms·

271.
by cfallin 12y ago
Sure, but I think this is just reiterating the original point that hardware is cheap and programmers are expensive. If you need to meet a performance goal and hardware is cheap but programmers are expensive, then throw hardware at it. The p
272.
by cfallin 12y ago
Yep, or even your own time if you run the program multiple times. E.g., if your code is running on a thousand machines, that CPU-hour savings that cost $0.05 now costs $50.00; past a certain point it does pay to throw engineers at insane
273.
by cfallin 12y ago
Their Austin location is where they do their CPU design (or at least large parts of it), from what I've heard.
274.
by cfallin 12y ago
Add to that list Fred Brooks (IBM System/360, Brooks' Law): http://www.cs.unc.edu/~brooks/Toolsmith-CACM.pdf Relevant quote: "... the scientist builds in order to study; the engineer studies in order to
275.
by cfallin 12y ago
"RAM" here means SRAM (static RAM). That just means "array of storage elements (latches) connected by bitlines and wordlines", which is way more efficient than "random latches we scattered throughout the chip".
276.
by cfallin 12y ago
Yes, renaming exists in modern cores, but where do you think the physical values are stored? Answer: there's still a "physical register file". The renamer maps logical register slots to PRF entries. This is well-covered in ac
277.
by cfallin 12y ago
I see it more as "refuse to add the wrong features". The key to scaling IMHO is to avoid the ball-of-mud where every feature interacts with every other feature, making the design impossible to disentangle and modify sanely. In sof
278.
by cfallin 12y ago
I can totally relate to the instinct to plan things, and "do it right" the first time. Life is short; your 20s are shorter; don't waste them! At the 'wise old' age of 26, though, after changing paths twice (PhD drop
279.
by cfallin 12y ago
Modula-3: SPIN operating system from University of Washington: http://en.wikipedia.org/wiki/SPIN_(operating_system) . This one is another example of security-through-safe-languages-in-kernel-space.
280.
by cfallin 12y ago
> Why can't there be a different option to emit a compiler error whenever -fsanitize=undefined would cause the compiler to add program-crashing code? The simple answer is "the halting problem". If you can build a compiler
281.
by cfallin 12y ago
Actually, all else being constant, 5x voltage yields 25x power: P = CV^2 * f (multiply by activity factor if pedantic; assuming all transistors toggle every cycle here.)
282.
by cfallin 12y ago
Yes, the Bing example seems to give real-world validation of all this. In general it seems that hardware vs. software fit is orthogonal to concerns such as frequent reconfiguration. Some algorithms simply match hardware well (high concurren
283.
by cfallin 12y ago
A big advantage that FPGAs have over ASICs, aside from time-to-market and one-time (fab) costs, is reconfigurability. Take a few seconds to stream in a new bitfile and suddenly you have a different chip. This seems like an obvious need in s
284.
by cfallin 12y ago
The best advice I ever got when I started to play with Verilog and FPGAs in undergrad was that one should think of the circuit first, then write the Verilog to describe it. As another poster said, this isn't programming; there are no u
285.
by cfallin 12y ago
> I have been trying to find decent Indian food, for example Tamarind on North Craig Street in Oakland? Oh how I miss Pittsburgh... I was there four years and it took a little while but it really, really grew on me. I hope you find more
286.
by cfallin 12y ago
That sounds like a tricky/interesting problem -- out of curiosity, what's the higher-level problem you're trying to solve? What are the required semantics? For CMC, synchronizing with the destination core is probably necessar
287.
by cfallin 12y ago
Fair point -- for cross-modifying code (one core's stores affect another core's fetch), this may be true. For self-modifying code, though (same core doing the store and fetch), the semantics are strong. See the Intel Developer Man
288.
by cfallin 12y ago
It's actually part of the architectural definition, so Intel could not change this without breaking ISA compatibility. And they take x86 compatibility very seriously!
289.
by cfallin 12y ago
x86 self-modifying code semantics are actually quite strong relative to most other ISAs -- a store to the currently executing code-stream logically takes effect immediately, so you could in theory modify the instruction immediately followin
290.
by cfallin 12y ago
Yes, there would be huge practicality issues with a "wafer-scale" FPGA -- aside from propagation delays, as you note, the chip would have horrible manufacturing yield, because any defect anywhere on the wafer would produce a defec
291.
by cfallin 12y ago
Nope, the ISA power model is an input to their work. And on the underlying question, there's been recent academic work on this, e.g. in [1]. Common wisdom these days (among many people at least) is that the architecture (ISA) doesn&#x2
292.
by cfallin 12y ago
Not OP, but a thought anyway: these worldviews are sort of duals of each other, IMHO. You can consider a "noun" to be one instance of a verb's application, i.e., an action. For example, "send an email" or "purc
293.
by cfallin 13y ago
I've run into this a few times, too -- seems to have something to do with the termcap info for tmux's virtual term. FWIW, I was able to work around it with 'stty', e.g.: $ stty erase ^? to recognize DEL (ASCII 127, or ^?
294.
by cfallin 13y ago
Past the Patterson/Hennessy books, Shen/Lipasti's "Modern Processor Design" was really helpful to get a better sense of the implementation details of real chips, especially when you move past the 'conceptual&#x
295.
by cfallin 13y ago
Mutability/immutability goes pretty deep philosophically... all of those projects are basically built on persistent data structures, but persistent data structures can be seen as just one type of "making time explicit". In ot
296.
by cfallin 13y ago
I did grad school in computer architecture and did a lot of cycle-level debugging in simulators, and I agree this mode of debugging is very very useful. I think that the closest analogue to a waveform view in software may actually be printf
297.
by cfallin 13y ago
From the first line of the source, it's a PIC (microcontroller) program, rather than something for x86 (which VirtualBox and friends emulate), so, no. There are a few open source PIC simulators -- e.g. [1] -- and I would guess you migh
298.
by cfallin 13y ago
I'll throw my vote in for the Kinesis Advantage along with the others. It made a huge difference, especially for Emacs pinky. The thumb keys are wonderful and make so much more sense than wasting both thumbs on a spacebar. As a datap
299.
by cfallin 13y ago
The bitcoin mining analogy on p. 2 is actually pretty good IMHO -- I've tried to explain Bitcoin to others before but it always gets a little abstract when explaining proof-of-work.
300.
by cfallin 13y ago
You have a good point, over the long run the payout and cost should reach equilibrium because of the difficulty adjustment. However, that's assuming the mining hardware is commoditized and widely available (everyone has the most energy

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