camel-cdr

7 ms·

61.
by camel-cdr 4mo ago
Isn't HTML and CSS already a huge surface to support, unless you are happy with a subset?
62.
by camel-cdr 4mo ago
> i wish there was just an SDK for building apps (i'll vibe code towards a great epub experience, i'm fine with that) That seems to be what crosspoint-reader is: https://github.com/crosspoint-reader/crosspo
63.
by camel-cdr 4mo ago
I skimmed over the project a bit. It seems quite ambitious to aim to reimplement epub, considering that means supporting HTML, CSS, SVG and JavaScript. Is there a ebook format that isn't just build arround the concept of a webbrowser?
64.
by camel-cdr 4mo ago
> unless you're irresponsible enough to connect an LLM to something that actually matters Remember when people said Artifical Intelligence woun't be dangerous, because nobody will be stupid enough to give it free access to the
65.
by camel-cdr 4mo ago
This is not the correct analogy, because we know that they explicitly used a huge ammount of pirated books and other works.
66.
Felix86 26.06: Some Gaming(felix86.com)
3 points by camel-cdr 4mo ago|0 comments
67.
by camel-cdr 5mo ago
> Simplicity in the CPU hardware may reduce the probability of hardware bugs, but it increases the probability of software bugs, because the missing hardware features must be implemented at a much greater cost in software, like in the ca
68.
by camel-cdr 5mo ago
Porting this optimization to RISC-V Vector is pretty trivial.
69.
by camel-cdr 5mo ago
There are a lot more ARM extensions than people are aware of. E.g. debian uses ARMv8-A with FEAT_FP and FEAT_AdvSIMDas a base. Yes, floating-point and SIMD are optional in ARMv8-A, as are the following ISA extensions, only including ones th
70.
by camel-cdr 5mo ago
> From a bystanderʼs POV it is excessively hard to memorize all the mess with multiple different extensions It's the same for other ISAs. > What Iʼm slightly confused for is that all these extensions, useful for a minor part of a
71.
by camel-cdr 5mo ago
> Also, let's stop with the "vector length agnostic" types being the sole option for SVE extensions They aren't, see the `arm_sve_vector_bits` attribute. > I'm fine with recompiling my code, I do it every day
72.
by camel-cdr 5mo ago
greater then 512-bit SIMD isn't currently and in the near future relevant for regular general purpose processors. But for smaller more specialized CPUs in embedded or automotive usecases you can get more parallel compute, while keeping
73.
by camel-cdr 5mo ago
In GPUs GLSL like types compile down to what basically is variable length SIMD. A vec4 doesn't get compiled to a SIMD vector with four floats, but rather to four SIMD vectors, each containing N FP32 elements (usually 32 or 64). Look at
74.
by camel-cdr 5mo ago
Looks like that isn't a portable SIMD abstraction, but more similar to adding architecture-specific SIMD intrinsics support to go, with nicer syntax.
75.
by camel-cdr 5mo ago
> This will take decades because you cannot change existing architectures/processors. I think once, AVX-512, SVE and RVV are wide spread enough, you'll have a rather powerfull baselevel you can target. But this will take a lot
76.
by camel-cdr 5mo ago
Here is a highway example: https://gcc.godbolt.org/z/7sdPr61W6 There is a bit of boilerplate to get dynamic dispatch working, but apart from that it's quite simple to use.
77.
by camel-cdr 5mo ago
Ah, so you're just doing SoA or AoSoA layout? It sounded like you where doing something more special than the standard SIMD usecase. This does easily work with SIMD abstractions and even length-agnostic vector ISAs, unless you're
78.
by camel-cdr 5mo ago
So you "just" write 4 assembly implementations?
79.
by camel-cdr 5mo ago
CNT and CNTP don't seem to be optional for SVE, from what I found. (unless you mean HISTCNT) It seems to me like you want tp use CNTP on a bitset that tells you, which rows are relevant, skipping them if CNT is 0? Is that what you wher
80.
by camel-cdr 5mo ago
OK, I thought it couldn't be that, because that should be doable with std::simd or a SIMD abstraction. Well, unless you JIT it, in which case intrinsics wouldn't help either. > You can match search patterns across a random doze
81.
by camel-cdr 5mo ago
IMO what's needed is ISPC like guided autovec with a lot of hinting support to control codegen (e.g. hint for generating an unrolled version only or an unrolled and non-unrolled version). Basically something like #pragma omp SIMD, but
82.
by camel-cdr 5mo ago
> There was a real alternative being considered at the time: integrating ISPC-like semantics natively in the language. I think this is the best solution for truely portable SIMD. Sure it doesn't cover everything, but it makes autove
83.
by camel-cdr 5mo ago
> Trying to abstract over SVE with a SIMD library is a bit of a fool's errand It reallt isn't. You just make the default SIMD-width agnostic and anything less portable opt-in. You can still specialize for a specific width pn sc
84.
by camel-cdr 5mo ago
I don't quite get how something like highway doesn't cover this, while intrinsics do. Can you explain the usecase more concretely?
85.
by camel-cdr 5mo ago
The data layout can often be done dynamically based on your target architecture.
86.
by camel-cdr 5mo ago
If I got magically handed the perfect rust rewrite for a project of this magnitude, it would take way longer than 9 days to merge, because I would need to make sure it's actually good.
87.
by camel-cdr 5mo ago
The website says RVA23, if you click on read more. It still seems quite vague, but to give them some credit, they did spend 17K € to sponsor RISC-V Summit Europe 2026. Well probably hear more from them there.
88.
Preliminary in-progress RISC-V "P" Extension(github.com)
2 points by camel-cdr 6mo ago|0 comments
89.
by camel-cdr 6mo ago
bitfield insert/extract was also looked at by the scalar efficiency SIG: https://lists.riscv.org/g/sig-scalar-efficiency/topic/115060... IIRC it didn't go anywere, because it wasn't worth the e
90.
by camel-cdr 6mo ago
pext/pdep are incredible, I'm hoping to see them in more SIMD ISAs in the future. But my favorite is the 8x8 bit matrix transpose SIMD instruction (gf2p8affine, which does a bit more, buy I care about the tranapose). Combined with

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