brucehoult

6 ms·

31.
by brucehoult 2mo ago
They have never been annoying to type on a Mac.
32.
by brucehoult 2mo ago
I've been posting my writing on the internet since 1990, from a Mac where we all learned how to make en and em dashes, umlauts, accents, degree symbols, proper single and double quotes, and so forth from Day #1 and I have absolutely no
33.
by brucehoult 3mo ago
Also a user-programmable 300 MHz 8051 (8 bit) primarily there to manage timers and interrupts and wake up the big 64 bit cores. Note that the application-processor 1 GHz C906 and Arm A53 are either/or, you can't run both at the sa
34.
by brucehoult 3mo ago
Don't forget the 128 bit vector ISA with 32 registers, supporting up to 64 bit int and FP, and with LMUL=8 you can process 1024 bits with a single instruction (at 3 cycles per 128 bits for most operations). Fully supported by GCC and
35.
by brucehoult 3mo ago
I've never read any of his economics (didn't know until today that he was one) and formed an opinion based only on his tech press writing. Interesting that he was on the board of TSMC! > I suspect his economic ideas were more p
36.
by brucehoult 3mo ago
Pournelle was good as a kind of (relatively) non-technical user in the early days (70s, early 80s) who just wanted to use computers to write books. Dvorak was quite good, but for me much too oriented towards the Wintel world. And then there
37.
by brucehoult 3mo ago
We have RISC-V. Software binary compatibility is less important now than it has been for 30 or 40 years of x86 dominance because now we are so over-served by hardware that most software runs just fine in emulation (especially transpiling&#x
38.
by brucehoult 3mo ago
> Why can't anyone build a performant RISC-V cpu? "They" can, and are. Many "they"s. > I'm starting to get the feeling that there is something fundamentally broken in the RISC-V specification that fundame
39.
by brucehoult 3mo ago
We have no idea at all what the terms are.
40.
by brucehoult 3mo ago
> Finally the chips have to deliver in performance, to actually provide good mobile devices There were still, as recently as 2025, new smartphones being released with only Arm A53 cores from 2012. Low end, obviously, but equally obviousl
41.
by brucehoult 3mo ago
> Why not just switch to a slightly different compiler and core, and then you make all your old code safe without verifying it You don't even need a new core. Fil-C makes regular old (and new) C code memory-safe. You can use it for
42.
by brucehoult 3mo ago
QEMU. Docker, using QEMU under the hood, there automatically with Docker Desktop on Mac & Windows, install QEMU yourself on Linux and configure binfmt_misc to use it.
43.
by brucehoult 3mo ago
The THead C906 core is full Linux-capable but is microcontroller-adjacent and has an early draft version of RVV that is different in details but has the same flavour (and at least some code is binary-compatible with RVV 1.0). Recent GCCs RV
44.
by brucehoult 3mo ago
> "arm removing thumb" should have been a strong signal. I don't see any reason to think that Arm ISA designers are any more skilled and knowledgable than RISC-V ISA designers. Given the relative number of people and the a
45.
by brucehoult 3mo ago
I disagree.
46.
by brucehoult 3mo ago
The performance gap between RISC-V and x86 or Arm is in fact closing. The SpacemiT K3 machines which most people who ordered in early May have now received are comparable to the RK3588 and Pi 5, with Rock 5 delivered to customers in mid 202
47.
by brucehoult 3mo ago
You can't remove C from future RVA because a large part of the value of RVA is that each version can run all the shrink-wrapped (binary distribution) code built for the previous versions.
48.
by brucehoult 3mo ago
Self-evidently, you therefore won't be the person building this machine.
49.
by brucehoult 3mo ago
> small cores are arbitrarily given a burden of supporting variable-length instructions Even the smallest commercial microcontroller cores e.g. the CH32V003, support the C extension. They strip out other things, such as half the intege
50.
by brucehoult 3mo ago
x86 seems to get by. And how is an instruction spanning a page boundary and causing a page fault any worse than an instruction NOT spanning a page boundary and the next instruction causing the page fault instead? As Paul said, if a 4 byte i
51.
by brucehoult 4mo ago
The referenced article specifically says $4000, but reading it more carefully now that's the UPGRADE price, not the full price of the machine. Checking also... https://www.macrumors.com/2026/03/05/mac-stu
52.
by brucehoult 4mo ago
They use the GPU but an Apple Silicon GPU has the same high speed access to all the RAM on the machine as the CPU does, rather than having its own walled-off maybe 16 GB VRAM in mainstream gaming GPUs or 24 GB in RTX 4090 or RTX 5090 (MSRP
53.
by brucehoult 4mo ago
A Mac is cheaper than a high end GPU with the same amount of RAM.
54.
by brucehoult 4mo ago
I don't know what kind of code sysbench is using, but I get far better with a very simple `memcpy()` loop: See https://news.ycombinator.com/item?id=48523343
55.
by brucehoult 4mo ago
I don't know how they got their 3 GB/s memory bandwidth. My own testing shows 5347.7 MB/s on a 64 MiB to 64 MiB `memcpy()` using a basic 7 instruction RVV copy loop an X100 core. That's a total 10.7 GB/s memory band
56.
by brucehoult 4mo ago
See: https://github.com/brucehoult/k3_ai Or my longer top level comment. Unlike a GPU or NPU, you can just run all your normal RISC-V Linux programs on the AI cores. Bash, gcc, emacs, nodejs ... whatever you want. It&#
57.
by brucehoult 4mo ago
> That documentation also seems to be the original source of the marketing claims that the K3 provides 60 TOPS of AI compute and can run 30B models at over 10 tokens/s. Well, sort of– as another spoiler, I can share that I hit a har
58.
by brucehoult 5mo ago
Yeah, in 20 years instead of 100 years. I'm going to replace it before then.
59.
by brucehoult 5mo ago
> instead of a PDP 11 as the virtual machine, why not risc V What would that look like, in your view? I can't see them being significantly different, as computation models go. And I'm familiar with both. If you're thinking
60.
by brucehoult 5mo ago
They've finally stopped comparing RISC-V boards to Pi 3! But why don't they include Pi 3 and Pi 4 in the charts *anyway*, as well as come more appropriate x86 machines such as Core2Duo, i7-860 (or other Nehalem), 2nd-5th gen i5 et

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