brucehoult

34 ms·

1. 361.▲
   by brucehoult 2y ago

   You can do that on modern CPUs, and I do. If you can't do it, it's simply because you haven't studied the CPUs closely enough. I write compilers, and I write critical routines by hand when compilers don't do a good job
2. 362.▲
   by brucehoult 2y ago

   Counting instructions is problematic. 6502 has 56 mnemonics, RV32I/RV32E has 37. But mnemonics are arbitrary. Are BCC, BCS, BEQ, BMI, BNE, BPL, BVC, BVS really different instructions, or just one instruction with a field specifying the
3. 363.▲
   by brucehoult 2y ago

   It's kind of hard to get hold of a PDP-11 these days. Even getting an OS, compiler etc is not that easy. If you like the PDP-11 then you get the same qualities slightly restricted in the MSP430 and slightly enhanced in the 68000. But,
4. 364.▲
   by brucehoult 2y ago

   Lol. I've been programming assembly language since 1980, on at least (that I can remember) 6502, 6800, 6809, 680x0, z80, 8086, PDP-11, VAX, Z8000, MIPS, SPARC, PA-RISC, PowerPC, Arm32, Arm64, AVR, PIC, MSP430, SuperH, and some propriet
5. 365.▲
   by brucehoult 2y ago

   That was never about the instruction set, it was more about the operating system -- or lack of one. As for modern CPUs and OoO etc, that's only about performance. The CPU, no matter sophisticated, must produce exactly the same result
6. 366.▲
   by brucehoult 2y ago

   No, my argument is that even if load with scaled indexed addressing takes a cycle longer, it's a rare enough thing given a good compiler and, yes, in many cases vector/SIMD processing, that you are very unlikely to actually be abl
7. 367.▲
   by brucehoult 2y ago

   Yes I'm well aware. I have a 65C02 on a breadboard. I have a 6809 on a breadboard. I've seen all Ben's videos. The *only* advantage the 6502 has is the exposed and non-multiplexed address and data busses, which you can single
8. 368.▲
   by brucehoult 2y ago

   > modern RISC architectures such as ARM, MIPS or RISC-V. At some point, a serious assembly programmer should definitely learn some of them. Yes. > However, they are not ideal to start with: the “S” in RISC stands for “simple”, but the
9. 369.▲
   by brucehoult 2y ago

   It's $8 and can't run without external ROM and RAM and a clock circuit and some glue logic. A RISC-V CH32V003 32 bit processor with 2k RAM and 16k of flash running at 48 MHz costs $0.10 for an 8 pin package (6 available I/O p
10. 370.▲
    by brucehoult 2y ago

    Ok, there exist cores that don't have a penalty for scaled indexed addressing (though many do). Or is it that they don't have any benefit from non-indexed addressing? Do they simply take a clock speed hit? But that is all missing
11. 371.▲
    by brucehoult 2y ago

    Yes, I've had my VF2 for two years exactly, this week. Until the P550 Megrez arrives, hopefully in the next week, the VF2 is still the fastest RISC-V board I have for software development. It builds everything I've tried faster th
12. 372.▲
    by brucehoult 2y ago

    The criticisms there are at the same time 1) true and 2) irrelevant. Just to take one example. Yes, on ARM and x86 you can often do array indexing in one instruction. And then it is broken down into several µops that don't run any fast
13. 373.▲
    by brucehoult 2y ago

    No, that's when they open sourced it. It was designed in 2018/early 2019 and picked up the May 2019 RVV spec. By late 2021 I already had a commercially sold C910 dev board (RVB ICE). https://linuxgizmos.com/dev-kit
14. 374.▲
    by brucehoult 2y ago

    Hopefully the RuyiBook will be great but it's hardly a "small RISC-V processor". The ~$5 Milk-V Duos are great. Two C906's, one with MMU and vectors etc for running Linux and one without those for "microcontroller&q
15. 375.▲
    by brucehoult 2y ago

    Which is exactly what many people want. OP said "small processor"
16. 376.▲
    by brucehoult 2y ago

    The 16 registers in RV32EC [1] on the CH32V003 is not a lot using the standard ABI once you take out the zero register, return address, stack pointer, globals pointer, and thread pointer [2] you're left with 11 registers, allocated as
17. 377.▲
    by brucehoult 2y ago

    > First semester: mostly concentrated on 6502 with a full 6502 CPU emulator as the final project. I like the principle, and the 6502 holds a special place in my heart as my introduction to machine code programming on an Apple ][ in late
18. 378.▲
    by brucehoult 2y ago

    This was previously posted as https://news.ycombinator.com/item?id=42882360
19. 379.▲
    by brucehoult 2y ago

    I have two points here: 1) It's a great pity an in-order RISC-V machine similar to A55 was not tested -- the obvious choice being SiFive's own U74 core which in the JH7110 is probably the most common RISC-V SBC and laptop SoC of t
20. 380.▲
    by brucehoult 2y ago

    Of course you can exclude them, to determine whether the aircraft themselves are a viable commercial proposition for the people who bought them (the airlines) -- which they were, just as other aircraft such as the A380 today are. The people
21. 381.▲
    by brucehoult 2y ago

    I didn't overlook development costs, I SPECIFICALLY excluded them, and SAID that I was doing so.
22. 382.▲
    by brucehoult 2y ago

    I downloaded both the 6.3 and 6.4 RISC-V binaries and ran them on my 1.6 GHz Lichee Pi 3A, which has the SpacemiT K1 SoC. 6.3: 71 single core, 327 multi core 6.4: 133 single core, 545 multi core The 6.3 results are in line wit
23. 383.▲
    by brucehoult 2y ago

    Concorde at least made more money than it cost to operate (and maintain). The TU-144 made 102 commercial flights, with 55 of those carrying passengers -- the others I assume were cargo. Not 102 flights per day or month -- 102 flights TOTAL
24. 384.▲
    by brucehoult 2y ago

    popup-based authentication does not actually need high performance.
25. 385.▲
    by brucehoult 2y ago

    > This is needlessly aggressive. I apologise. > I specialize in writing SIMD code. That is my job. I am very eager to get my hands on a RVV chip The P550 core was announced in June 2021, 2 1/2 years ago. It was stated at the time
26. 386.▲
    by brucehoult 2y ago

    Actually Eswin doesn't seem to claim B extension: https://www.eswincomputing.com/en/bocupload/2024/06/19/17187... But Intel Horse Creek did (and also was higher MHz, they said 2+ GH, but I thin
27. 387.▲
    by brucehoult 2y ago

    Oops! You're right. They only claim RV64GBC https://www.sifive.com/document-file/p550-core-data-sheet Although that was at announcement in June 2022. SiFive have continuous improvement and quarterly updates, which
28. 388.▲
    by brucehoult 2y ago

    > Why are these only 1.4ghz frequency, when raspberry pi gets to 2.4ghz? Milk-V Megrez is shipping the same SoC running at 1.8 GHz. Intel's Horse Creek chip with the same cores ran at 2.4 GHz, but Intel is in trouble and cancelled n
29. 389.▲
    by brucehoult 2y ago

    Nothing except the Pioneer (and now this and the Milk-v P550) has L3 cache. BPI-F3 (etc) has only 512 MB of L2 cache for each cluster of 4 cores, vs 2 MB on the VisionFive 2 (etc), and I think this is the biggest issue. Similarly the TH1520
30. 390.▲
    by brucehoult 2y ago

    > I was going to buy one of these until I realized it didn't have vector extensions A statement like this pretty much disqualifies your opinions. Why would you expect it to have vector extensions? No one has ever claimed it does, th