bXVsbGVy

11 ms·

1. 91.▲
   by bXVsbGVy 6y ago

   AFAIK, none. Recently Lattice updated their licensing forbidding reverse engineering, but changed their mind once the community complained. Also, a while back, lattice added support to something that was already implemented on the open sour
2. 92.▲
   by bXVsbGVy 6y ago

   The vendors tools are notoriously buggy, don't conform to the HDL standard and lacks support to inference of some functional block (cascade DSPs and FIFOs for example). Some FPGAs features are only available on yearly paid subscription
3. 93.▲
   by bXVsbGVy 6y ago

   > Anticipate future decisions, pre-load instruction, chose best path through the CPU. This slide is about speculative execution not necessarily about branch prediction.
4. 94.▲
   by bXVsbGVy 6y ago

   AMD Zen 2 CPU and IBM z15 mainframe claims to be using TAGE branch predictor -- but this doesn't say much. The basic TAGE is quite simple (see [1]), but actual implementation likely includes loop predictor, statistical corrector predic