andreiw

18 ms·

121.
by andreiw 10y ago
Not ARM64 ports. Important difference. But yes, you can go download an ISO now and boot on any ARM64 server. Cool stuff.
122.
by andreiw 10y ago
No, it wouldn't. Sometimes I wonder if IA-64 was just an exercise in killing of Alpha and HP-PA... Anyway, x64 succeeded because instead of producing something no one asked for, and poorly (IA-64), AMD went to Microsoft, found out what
123.
by andreiw 10y ago
Not true. When multiarch mattered (NT 3 and 4), Microsoft was the only vendor that delivered the exact same OS, device support and development environment across x86, Alpha, MIPS and PowerPC, and pushed the industry towards standardization.
124.
by andreiw 10y ago
And yet the Snapdragon has nothing to do with any shipped or to be shipped ARM server parts...
125.
by andreiw 10y ago
The ARM server chips are not related to their mobile counterparts. Pretty much everyone is doing a custom microarchitecture, instead of growing mobile designs or building on ARM's own IP. The 2017 chips (3rd generation) are Xeon E5 com
126.
by andreiw 10y ago
Which chips are you refering to, specifically? Because otherwise it's a blanket statement that is simply untrue.
127.
by andreiw 10y ago
Actually, the only signal so far is to AMD to continue investing developing ARM chips after the A1100.
128.
by andreiw 10y ago
No, this is the real deal, apparently. Obviously the work has gone on for years but between OCP and Xeon competitive chips (ThunderX2 and Centriq) it makes sense to put public weight behind it. The real question is if WSL (Ubuntu for Window
129.
by andreiw 10y ago
Time and time? We do see them in Linux. The ARM server ecosystem has been in the works for a few years. TechCon'16 we saw the announcement that the software is fully there: and this is not hype, all major distributions support all the
130.
by andreiw 10y ago
The government should do my taxes. No, seriously. They already know enough to figure out if I made mistakes in my tax return, so there's no real utility here, beyond giving every tax payer the ammunition to land themselves in hot water
131.
by andreiw 10y ago
So ARMv7-A is still, like, a thing?
132.
by andreiw 10y ago
non-volatile memory tech, e.g. NVDIMM
133.
by andreiw 10y ago
This is an important realization and will become even more so as we transition toward NVM. I hit this realization partially about 7 years ago developing a custom loopback disk driver, capable of handling different image formats. I'd ha
134.
by andreiw 10y ago
Toxic behavior 101. One dude, who I am sure most people never heard of, spouted off about some demo code written decades ago by a guy that is the quintessential successful software engineer and that everyone knows about, probably even lit
135.
by andreiw 10y ago
I tried to look something up but there is no mention of underlying tech... is this at all related to PTP?
136.
by andreiw 10y ago
- Going with the gut instead of listening to others. I had the surrealistic experience of a bunch of extremely senior folks around a company telling me not to join a team I had done a project for. I should have listened, esp. in light of th
137.
by andreiw 10y ago
Does anyone know if the GPU can then be passed thru to VBox or Fusion?
138.
by andreiw 10y ago
Now rewrite in IR =))
139.
by andreiw 10y ago
Not really. IR is exactly a good fit for compiled languages, because there are no "hard to translate" idioms in languages targetted by LLVM that need really orthogonal translations on different architectures, which by the way aren
140.
by andreiw 10y ago
That's all fair and correct, but the amount written for, say, an OS, in assembly - native or IR - is quite minimal and well-controlled, usually written in assembly because of a good reason (exception handlers, for example). At that poi
141.
by andreiw 10y ago
The other thought I had here, is that AFAICT IR is not a standard. There is no requirement that it remains compatible in 50 years or 5 months. There is no standard IR, and shouldn't be, as that would become an impediment to compiler ev
142.
by andreiw 10y ago
In this way, IR would fullfil the same role Macro-32/64 did for porting VMS to Alpha and beyond. However, it appears to my understanding (sorry, I was still crawling when VAXes were on the way out), that the benefit was retaining &quot
143.
by andreiw 10y ago
Yeah, I think something like dlopen/dlsym, but stand-alone, and supporting ELF/PE32+/Mach-O binaries (both objects and binaries, shared objects, PIC and non-PIE) on any OS/architecture could be very useful. Even foreign
144.
by andreiw 10y ago
wat? v8.2 is out and soon in products, v8.3 has been announced. What do you consider to be very complex, if you throw away 32-bit support? What specifically do you consider to be "screwed up", beyond the virt hole with cntfrq_el0,
145.
by andreiw 10y ago
FWIW 64-bit ARMv8 is clean as well, designed without all the weird baggage that came with the 26->32 legacy ARM architecture. More importantly, ARM had reduced the impedance mismatch with x64, making porting various kinds of software (in
146.
by andreiw 10y ago
Except it is not the MS-DOS prompt (unless you actually ran command.com, via the NTVDM). It may look like a duck, quack like a duck (sort of), but it really was just another Win32 (albeit console) program.
147.
by andreiw 10y ago
You know what I just realized? Apple could have made the power port simply be recessed a bit...that way you could either plug in a USB-C device or a cable like this and not wind up with a wart (that the laptop can still fall on and thus bre
148.
by andreiw 10y ago
That might be the entire mobile ecosystem (although that sounds too simplistic, still, you are forgetting Linaro), but the ARM ecosystem also includes M-profile (deep embedded), R-profile (RTOS) and server-class (SBSA and "almost&quot
149.
by andreiw 10y ago
Why only 2GB? Especially for a device that's not shipping yet. I understand there might be SoC limitations, but I would be really surprised if the A64 cannot support 3 or 4GB. A53 is a bit on the slow side, but the worst part is that i
150.
by andreiw 10y ago
And yet a weaker memory model (as well as explicit cache and TLB maintenance) remove a major glass ceiling from both theoretical chip performance, practical perf/watt and silicon design and manufacure costs.

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