alexvoica

19 ms·

181.
by alexvoica 12y ago
Not really - and if they are, they are usually biased. You can try this: http://www.ece.gatech.edu/academic/courses/ece2035/readings/...
182.
by alexvoica 12y ago
This is the first board in a series of many. We have some very exciting things planned for the future.
183.
by alexvoica 12y ago
Everything should be on https://github.com/mips . Please have a quick look and tell me if there is something missing that you'd like to see.
184.
by alexvoica 12y ago
Here is quick breakdown: Newer/faster processor: 1.2 GHz dual-core MIPS32 vs. 700 MHz single-core ARMV6 More memory: 1 GB DDR3 vs. 512 MB DDR2 More storage options: 4 GB of flash + SD card expansion vs. microSD expansion Better connec
185.
by alexvoica 12y ago
We wanted a balanced feature set; things like USB 3.0 or Gigabit Ethernet can upset the low power mojo of a design.
186.
by alexvoica 12y ago
Because it's lower power.
187.
by alexvoica 12y ago
There are schematics available at http://elinux.org/CI20_Hardware/Documentation Is that enough?
188.
by alexvoica 12y ago
The kernel part is open while the user space is in binary blob form.
189.
by alexvoica 12y ago
We wanted a general purpose platform at a decent price and the SoC from Ingenic offered that - and more.
190.
by alexvoica 12y ago
We have documented our progress on eLinux http://elinux.org/MIPS_Creator_CI20 . http://elinux.org/CI20_upstream is probably the place to start.
191.
by alexvoica 12y ago
Please let me know if you have any questions.
192.
MIPS Creator CI20 development board now available for $65(blog.imgtec.com)
48 points by alexvoica 12y ago|42 comments
193.
by alexvoica 12y ago
Some context: SELTECH is a Japanese company that is well-known for creating hypervisors for NVIDIA Tegra and other high performance mobile platforms running Linux. SELTECH has now ported its new FEXEROX hypervisor to MIPS M5150, a microcont
194.
A fully featured Linux hypervisor running on a MIPS microcontroller(blog.imgtec.com)
3 points by alexvoica 12y ago|1 comments
195.
by alexvoica 12y ago
I don't know if you saw this MIPS-based dev board being announced http://blog.imgtec.com/powervr-developers/new-mips-creator-c...
196.
by alexvoica 12y ago
The new coherency manager that we've designed allows us to build up to 64 clusters of 6 cores each.
197.
by alexvoica 12y ago
For legacy, native non-MIPS code, we rely on binary translation.
198.
by alexvoica 12y ago
That was the first 64-bit RISC CPU, indeed. I think we can also claim first 64-bit CPU - but not 100% sure.
199.
by alexvoica 12y ago
Yes, I think that he might not be familiar with how DMIPS works (or what it is).
200.
Implementing hybrid ray tracing in a rasterized game engine(blog.imgtec.com)
2 points by alexvoica 12y ago|0 comments