adrian_b

57 ms·

751.
by adrian_b 5mo ago
My point was that before the 1967 version, ASCII had no influence whatsoever on the design of computer architectures, because it was useful only for transmission on serial communication lines and it remained compatible with the use of 6-bit
752.
by adrian_b 5mo ago
That document referred very clearly to ASCII (the 1967 variant), by "seven-bit code proposed by the International Standards Organization". There was no other character set that could be referred to by these words. Probably at the
753.
by adrian_b 5mo ago
If the videos are indeed so old, then probably they were not intended for customers but for the internal training of IBM employees, which would match the "CONFIDENTIAL" label.
754.
by adrian_b 5mo ago
The Olympus CPU cores demonstrate a great improvement over any previous Arm-based server CPU cores. Nevertheless, when browsing the results, there are several things that must be kept in mind: 1. Much of the advantage of the NVIDIA Vera CPU
755.
by adrian_b 5mo ago
IBM System/360 normally used the IBM EBCDIC 8-bit character set, which was designed simultaneously with the decision to use 8-bit bytes, before the launch of System/360. All the IBM computers older than System/360 had used 6-
756.
by adrian_b 5mo ago
The calculator chip 4004 never had any relevance for computers, and it did not have "bytes". Intel 8008 did not have anything original in its architecture, it was just a monolithic PMOS re-implementation of the CPU of the embedded
757.
by adrian_b 5mo ago
Why do you think that the presentation was done in 1964? On Youtube there is no mention about the date. OS/360 was announced in 1964 but it was first delivered more than a year later. I doubt that such presentations were done about a p
758.
by adrian_b 5mo ago
This kind of things can certainly be run locally, even on a small mini-PC, like a NUC, or even on a laptop, with the weights stored on SSDs. Like I have said, the problem is not that they cannot be run, but that they may run more slowly tha
759.
by adrian_b 5mo ago
There is no wear on the SSDs, because the weights are just read, they are not written during inference. For model training, the requirements are very different, and the training of a big LLM cannot be done with home equipment. On the other
760.
by adrian_b 5mo ago
This may be true about any models hosted by others than you. At least the Xiaomi models are open weights and you can host them yourself, avoiding such concerns.
761.
by adrian_b 5mo ago
The difference between datacenter hardware and cheap personal hardware is not in what can be run and what cannot be run. Anything can also be run on a cheap computer. The difference is in speed. A cheap computer may run a big model up to a
762.
by adrian_b 5mo ago
Depends on what you mean by "economically feasible". Even very cheap mini-PCs and laptops can run any of the models run by cloud providers, albeit at a much lower speed (i.e. with the weights stored on SSDs). Whether such a low
763.
by adrian_b 5mo ago
Switch in place is inefficient for data stored in memory, like a matrix. The most efficient way to swap 2 values stored in memory is to use 2 load instructions and 2 store instructions, like "load X in R1; load Y in R2; store R1 in Y;
764.
by adrian_b 5mo ago
In C++, nobody would want or need to use virtual functions in high-performance computational applications, while in the C language structures with virtual function tables that are accessed explicitly by the programmer are in widespread use
765.
by adrian_b 5mo ago
Yeah, European. When I was a child, bullying happened, but it was infrequent. Teachers would punish it severely if reported, but snitching was considered rather shameful, so it was more frequent that bullying was handled by the weaker bull
766.
by adrian_b 5mo ago
Sad. When I was a child, I always had with me a multi-tool Swiss army knife, including at school, because I was very frequently building various things, or disassembling others to see how they were made. That early experience was very influ
767.
by adrian_b 5mo ago
While the results were not surprising, I found interesting that the number "69" was repressed in the output, so not even this kind of mathematical question escapes GPT censorship. It appears that recognizing the effects of censors
768.
by adrian_b 5mo ago
All Intel, AMD or Arm-based CPUs and any other modern CPUs have dozens of errata, even if some CPU vendors keep them secret, instead of publishing them, as they should. Fortunately, most of the erroneous behaviors are triggered only by very
769.
by adrian_b 5mo ago
Intel® Advanced Vector Extensions 10.2 Architecture Specification, Revision 5.0 Page 18: > 3.1 INTEL® AVX10 INTRODUCTION > ... > This ISA will be supported on all future processors , including Performance cores (P-cores) and Effic
770.
by adrian_b 5mo ago
AVX-512 increases energy efficiency and performance unconditionally, in all AMD Zen 4 and later CPUs and in all Intel Ice Lake and later CPUs. Only in the now obsolete Intel server and workstation CPUs from the Skylake Server, Cascade Lake
771.
by adrian_b 5mo ago
No, that has changed. About a half of year ago Intel has announced that they will mandate the 512-bit vector width and the full AVX-512 a.k.a. AVX10 support in all future CPUs, starting with Nova Lake. This includes all E-cores that will su
772.
by adrian_b 5mo ago
AVX-512, originally called the "Larrabee New Instructions" has been the only decent vector extension of the Intel-AMD ISA, which has been coherently planned instead of being a heap of more or less randomly chosen instructions, eac
773.
by adrian_b 5mo ago
I believe that the only useful form of the antique books, such as those originally written in Latin or Ancient Greek, is a bilingual edition, like those provided by the Loeb Library collection. For Euclid's Elements, there is this exce
774.
by adrian_b 5mo ago
I always use binary interchange formats between programs so I am not familiar with the overhead caused by format conversions. Even when displaying numbers for reading them, in the case of floating-point numbers that are displayed in the &qu
775.
by adrian_b 5mo ago
There already exists a large installed base of AMD Zen 4 and Zen 5 CPUs. Next year, these AVX-512 supporting CPUs will be joined by AMD Zen 6 and Intel Nova Lake. Starting with Intel Nova Lake, all future Intel CPUs will support AVX-512.
776.
by adrian_b 5mo ago
From all the workloads that I execute on my laptops or desktops, there is only one where the speed matters yet it is not significantly affected by the use of the AVX-512 ISA: the compilation of big software projects. All the other things th
777.
by adrian_b 5mo ago
Your comment is obsolete. AVX-512 had been discontinued in the CPU generations from Alder Lake until the Panther Lake, Wildcat Lake and Clearwater Forest CPUs introduced during the first half of 2026, but Intel has committed than all future
778.
by adrian_b 5mo ago
Some people, including the management of most big corporations, claim that verbal insults, which do no actual physical harm to anyone, are "unacceptable abusive behavior", while the actions that do physical harm to others, e.g. by
779.
by adrian_b 5mo ago
For reverse engineering, you still need access to the FPGA tools provided by the vendor, to see what changes in the bitstream when you change the design. If the bitstream is encrypted, you will not see the changes, so the only way is to rev
780.
by adrian_b 5mo ago
First of all, you already pay for the FPGAs, and the only reason why you pay for them is that they are "Field-Programmable" GAs. To be able to use the product that you own, as advertised, you MUST have the AMD software tools, beca

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