abbeyj

13 ms·

91.
by abbeyj 6y ago
I believe that this is included in the report generated by `powercfg /energy`.
92.
by abbeyj 6y ago
How would you use ARP here? ARP lets you find a MAC address assuming that you already know the IP address that you want to talk to. But without static IPs you wouldn't know the IP address of the phone that you're interested in.
93.
by abbeyj 6y ago
I was sure that I had read this story before but checking the date showed that this blog post was just published a few days ago. A little searching turned up the place that I had originally seen it: a comment on this very site. https:&#x
94.
by abbeyj 6y ago
It seems to be a CPU flag. This is managed by the kernel so that it is on for Rosetta 2 processes and off for everything else. See https://github.com/saagarjha/TSOEnabler
95.
Non-Generic Inner Functions(possiblerust.com)
2 points by abbeyj 6y ago|0 comments
96.
by abbeyj 6y ago
Tandy used the "TRS-80" name for many of their computer lines, even when they used completely different architectures. The original TRS-80 ("Model I"), the TRS-80 Model III, and the TRS-80 Model 4 all used a Z80. https
97.
by abbeyj 6y ago
Since the author is here and reading comments: when viewing this page in dark mode, some of the text is black-on-black. Specifically the "if" in "Compiling if-expressions, finally" and the "jcc" and "jmp&
98.
SiFive to Introduce New RISC-V Processor Architecture and RISC-V PC(businesswire.com)
22 points by abbeyj 6y ago|9 comments
99.
A stepping stone for measuring quantum gravity(rug.nl)
1 points by abbeyj 6y ago|0 comments
100.
by abbeyj 6y ago
https://en.wikipedia.org/wiki/Distribution_Media_Format
101.
by abbeyj 6y ago
For your second question, I believe those lines are explained a bit further down the page: "The reddish horizontal lines are remnants of the metal layer, which was removed for this photo. These lines carried the control signals, power,
102.
by abbeyj 6y ago
Do you know if NOP is really executed as `XCHG AX, AX` (as would be implied from its position in the opcode map and its cycle count) or if it is special-cased in some way? I've always been curious about the XLAT instruction. It perfor
103.
Reverse-engineering the 8086's Arithmetic/Logic Unit from die photos(righto.com)
102 points by abbeyj 6y ago|38 comments
104.
by abbeyj 6y ago
I think that this was the idea behind Norton CrashGuard. Intercept all faults and then try to skip past the faulting instruction. This worked ... sometimes. At least long enough for you to save your work and restart the program. But lot
105.
Those Win9x Crashes on Fast Machines(os2museum.com)
274 points by abbeyj 6y ago|102 comments
106.
Parentheses and Indentation(nl.movim.eu)
1 points by abbeyj 6y ago|0 comments
107.
C64 Turbo Assembler 34-Year-Old Bug Found and Fixed [video](youtube.com)
4 points by abbeyj 6y ago|0 comments
108.
by abbeyj 6y ago
Coreboot does something similar to this. Very early in the boot process the RAM has not yet been initialized and so cannot be used. You need to execute some code to set up the RAM before you can use it. One approach to handling this is t
109.
by abbeyj 7y ago
That's the approach taken by https://github.com/libcpu/libcpu . It supports 6502 and several other CPUs.
110.
Early Meme Site Ytmnd Has Been Resurrected with the Help of Fans(vice.com)
2 points by abbeyj 7y ago|0 comments
111.
Permanent magnets could be a solution for delivering fusion energy(phys.org)
3 points by abbeyj 7y ago|1 comments
112.
Debugging Gdb Using Rr: Ptrace Emulation(robert.ocallahan.org)
2 points by abbeyj 7y ago|0 comments
113.
by abbeyj 7y ago
I don't think it does. ESNI is the intended fix for this problem.
114.
by abbeyj 7y ago
In the past this may have worked. But it won't anymore since browsers have introduced partitioning by origin in their caches. https://www.jefftk.com/p/shared-cache-is-going-away.amp
115.
by abbeyj 7y ago
> Internally the 8086 was a 16-bit CPU but its memory I/O was only 8 bits wide. Did you mean 8088 here?
116.
Ransomware borrows vulnerable driver to remove security software(news.sophos.com)
2 points by abbeyj 7y ago|0 comments
117.
Avoiding gaps in IOMMU protection at boot(mjg59.dreamwidth.org)
1 points by abbeyj 7y ago|0 comments
118.
by abbeyj 7y ago
I'm assuming you meant "horizontal blanking interval" instead of "vertical blanking interval". But I don't think that's entirely correct either. Some games will change the registers while the beam is act
119.
by abbeyj 7y ago
This was pretty enjoyable. It reminds me a bit of "return true to win" ( https://alf.nu/ReturnTrue ). I think I cheated a bit on Level 7. I just copy-pasted the code that wrote to epochComms and changed it to writ
120.
by abbeyj 7y ago
I believe the "digits" above refers to decimal digits, not binary digits. RSA-240 has 240 decimal digits. A 1024-bit number should have 309 digits. So: 2^((309 - 240) / 5.5) = 5978

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