Taniwha

56 ms·

811.
by Taniwha 5y ago
I'll add these examples of how to make a clock from the Verilog 2k standard: always #half_period areg = ~areg; always c = #5 ~c; the @() portion is not intrinsically part of the always - it's just usually used there
812.
by Taniwha 5y ago
Always implies an outer loop, when you reach the bottom of the loop you go back to the top and do the original event wait again, but not until you've waited for the intermediate event waits In simulation this is easy to implement, but
813.
by Taniwha 5y ago
well if you're making a synchronous call you have to wait for the response which is likely as bad as a pipe flush (or worse, because you likely flood the pipe with a tight loop waiting for the response, or a context switch to do someth
814.
by Taniwha 5y ago
oh totally, but then you aren't "making a procedure call" you're doing something different. In this case your data is likely traversing the memory hierarchy far enough so that the message data gets shared (more likely t
815.
by Taniwha 5y ago
A little background - I've written a couple of Verilog compilers - you can have always statements with multiple events, protocol state machines a bit like: always @(posedge clk) begin do some stuff if (condition
816.
by Taniwha 5y ago
I think that really the hard part of learning to design chip stuff really is other stuff - understanding where/how to use storage (flops) and combinatorial logic - and simultaneity: how to handle things that happen at the same time. In
817.
by Taniwha 5y ago
At the core of any protection boundary crossing is likely going to be a pipe flush (throwing away of tens or maybe 100+ instructions) - post spectre/meltdown we all understand that speculating past such a point into a differently privi
818.
by Taniwha 5y ago
(this is a light derail but related) some of this design IS firmware - the lowest level bootstrap is encoded into an internal ROM - currently it's a very dumb bootstrap, a real implementation would boot from a number of possible source
819.
by Taniwha 5y ago
If you don't synchronise it's not an issue :-) but if you have 100+ instructions in motion at any one time creating a bottleneck at the end of every basic block would likely have a big effect on how things run. Normally we retire
820.
by Taniwha 5y ago
RISCV doesn't have condition codes, which makes building systems like this with lots of ALUs a lot easier, everything happens in the registerfile and the renaming system. It does have 'sticky' state bits for FP and I can see
821.
by Taniwha 5y ago
Sorry no, I've worked on VLIW CPUs and an (unreleased) x86 core. In general though MIPS and RISCV are similar sorts of RISC architecture, they make some of the same design trade offs (no condition codes for example), RISCV avoids some
822.
by Taniwha 5y ago
Next step up is probably a VU13P based board, there were a few on EBay a year ago ~$5k, almost bought one, but then bitcoin went up again ..... I'm hoping for a crypto crash ....
823.
by Taniwha 5y ago
No FP yet - that's about half (adds and multiplies) done - but no reason why not
824.
by Taniwha 5y ago
I think the way to think of ASIDs is as each being a separate address space - in effect if you have 15 bits of ASID you have 2^15 - 32k address spaces. One thing I've done in VRoom! which is an extension on to the RISCV spec is that if
825.
by Taniwha 5y ago
It's a personal project, but an expensive one (with very large AWS bills some months), needs a commercial sponsor to end up as a real chip you could put in real platforms and a real chip design team to build it
826.
by Taniwha 5y ago
Yes VRoom! with renaming has as many registers as it has commitQ entries plus the architectural ones. So 64/32 + 31 (integer) + 32 (fp) + 32 (vector)
827.
by Taniwha 5y ago
I think that one has to separate out architecture and implementation a bit, they're obviously a deeply intertwingled dance - but you have to start with the architecture and tweak from there to get the best result in the end - I'm
828.
by Taniwha 5y ago
err HN swallowed my * there as in: "(you can thank me for the '*' in "always @(*)")"
829.
by Taniwha 5y ago
I'll add that freq scaled Dhrystone (DMIPS/MHz) is a particularly useful number because it helps you compare architectures rather than just clocks - you can figure out questions like "If I can make this run at 5GHz how will i
830.
by Taniwha 5y ago
Yeah, I can imagine that being particularly easy to implement in VRoom! exceptions are handled synchronously at the end of the pipe (with everything before them already committed, and everything after flushed). Instructions that can convert
831.
by Taniwha 5y ago
the commitQ entries are smart enough to 'see' the commits into the architectural file and request the data from it's current location It does mean lots of register read ports .... but you can duplicate register files at some
832.
by Taniwha 5y ago
thanks I'll have a look - I'm not so interested in raw scores, more about relative numbers so I can judge different architectural experiments
833.
by Taniwha 5y ago
conditional CALL is MUCH harder to implement well - it's because the call part essentially happens up at the PC/BTC end of the CPU while at the execution stage what you're doing is writing the saved PC to the LR/etc and
834.
by Taniwha 5y ago
One other comment about why GPLing something is important for some like me - publishing my 'secrets' are a great way to turn them into "prior art" - you read it here first, you can't patent it now - I can protect my
835.
by Taniwha 5y ago
Well, everyone was building tiny RISCVs, I kind of thought "can I make a Xeon+ class RISCV if I throw gates at the problem ?" :-) Seriously though I started out with the intent of building a 4/8 instruction/clock decoder
836.
by Taniwha 5y ago
Not yet - I have a pretty generic combined bimodal/global predictor - there's a lot of research on BTCs - it's easy to throw gates at this area - I can imagine chips hitting 20-30% BTC in area just to keep the rest running My
837.
by Taniwha 5y ago
Great questions - I'm using an open source UART from someone else, an d for the AWS FPGA system I have a 'fake' disk driver plus timers/interrupt controllers etc So far I haven't needed USB/ether/PCIe&#x2
838.
by Taniwha 5y ago
I wrote a second, much more standard Verilog compiler (because by then there was a standard) with the intent of essentially selling cloud simulation time (being 3rd to a marketplace means you have to innovate) - sadly I was a bit ahead of m
839.
by Taniwha 5y ago
yes and no - there's a few issues here: 1 - architectural - RISCV has a nice clean ISA, it's adding instructions quickly, CMOV is contentious issue there - I'm not an expert on the history so I'll let others relitigate
840.
by Taniwha 5y ago
I'm just starting this week, I've recently switched to some use of SV interfaces and it does not like arrays of them - sv2v seems the way to go - but even without that yosys goes bang! somethings too big Vivado compiles the same s

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