Sesse__

17 ms·

331.
by Sesse__ 1y ago
Another bottle-of-wine riddle I have been interested in recently: Say you have B number of tastings and can use each to taste any mix of wines, and you know that exactly zero, one or two of the wines are bad/poisoned/whatever. How
332.
by Sesse__ 1y ago
What _is_ the big difference between CRITICAL_SECTION and a futex, really? I always assumed that futexes were meant to be pretty similar to CRITICAL_SECTION (mostly-userspace locks that didn't have fatal spinning issues on contention).
333.
by Sesse__ 1y ago
It's included with the kernel as distributed by upstream. Your distribution may choose to split out parts of it into other binary packages.
334.
by Sesse__ 1y ago
Hit enter on the symbol, and you get instruction-level profiles. Or use perf annotate explicitly. (The profiles are inherently instruction-level, but the default perf report view aggregates them into function-level for ease of viewing.)
335.
by Sesse__ 1y ago
I have uBO, they're still obscenely large.
336.
by Sesse__ 1y ago
> Normally you spin up a tool like vtune or uprof to analyze your benchmark hotspots at the ISA level. No idea about tools like that for ARM. perf is included with the Linux kernel, and works with a fair amount of architectures (includin
337.
by Sesse__ 1y ago
Hard disagree. I'd like word processors to not need ten seconds just to start up. I'd like chat clients not to use _seconds_ to echo my message back to me. I'd like news pages that don't empty my mobile data cap just by
338.
by Sesse__ 1y ago
You don't need AVX512BW for shuffle, SSSE3 will do. (Of course, if you want wider registers, you'll need the newer versions such as AVX2 or AVX512, but they don't shuffle cross-lane.)
339.
by Sesse__ 1y ago
I don't think I understand what you are saying. Anyway, if you are strapped for space, do not use a winner tree.
340.
by Sesse__ 1y ago
Yes, since the inner nodes duplicate information, it uses more space (roughly twice as much). I've found them generally most effective for things like merging 256 streams or doing Dijkstra with not super-many nodes (e.g. Contraction Hi
341.
by Sesse__ 1y ago
The fastest way of doing a heap I've found is generally: Don't. For many of the relevant operations (graph search, merging streams, etc.), you can do just as well with a winner-tree; it can usually be updated branch-free with min&
342.
by Sesse__ 1y ago
Yup, but it's a bit of a dance for bootstrapping, since they require you to already have delegated to them, but some TLDs require all NSes to be in sync and answer for the domain before delegating…
343.
by Sesse__ 1y ago
> Maybe it's time for a new current-day platform that's similarly "constrained" on purpose? You have the fantasy consoles, where Pico-8 is probably the most well-known example.
344.
by Sesse__ 1y ago
Many DNS providers also don't support having an external primary.
345.
by Sesse__ 1y ago
> a bloom filter look up is by hash, and given the relatively small set of words in english, it would be pretty easy for the server to reverse the hash sent to it. Thus a bloom filter wouldn't be very private. The typical use of a B
346.
by Sesse__ 1y ago
You mean, for those who couldn't be bothered to click the link under a joke.
347.
by Sesse__ 1y ago
The poster has a Zen 2, where this is only optimal for large copies. For newer Intel, glibc might indeed choose to use REP MOVSB more often.
348.
by Sesse__ 1y ago
The L1 cache is faster than the L3 cache. Does it need to be anything more complicated than that?
349.
by Sesse__ 1y ago
That doc is about visibility _outside the core_ (“globally visible”), so it's not what I'm looking for. Similarly, if I look up MOVNTDQ in the Intel manuals ( https://www.intel.com/content/dam/www/pub
350.
by Sesse__ 1y ago
Do you have any Intel references for it? I mean, Rust has its own memory model and it will not always give the same guarantees as when writing assembler.
351.
by Sesse__ 1y ago
A source on what? The Intel optimization manuals explain what MOVNTQ is for. I don't think they explain in detail how it is implemented behind-the-scenes. See e.g. https://cdrdv2.intel.com/v1/dl/getContent&#x2
352.
by Sesse__ 1y ago
You mean if you access it from a different core? I believe that within the same core, you still have the normal ordering, but indeed, non-temporal writes don't have an implicit write fence after them like x86 stores normally do. In any
353.
by Sesse__ 1y ago
There's an error here: “NT instructions are used when there is an overlap between destination and source since destination may be in cache when source is loaded.” Non-temporal instructions don't have anything to do with correctnes
354.
by Sesse__ 1y ago
Well, “bandwidth is expensive” is a true claim, but it's also a very different claim from “a [normal] caching server couldn't handle 56 Gbit/sec”…?
355.
by Sesse__ 1y ago
It really depends on the size of the active set. If it fits into RAM of whatever server you are using, then it's not a problem at all, even with completely off-the-shelf hardware and software. Slap two 40gig NICs in it, install Varnish
356.
by Sesse__ 1y ago
> We are talking about an insane amount of data here. It was 56 Gbit/s. This is not something a "caching server" could handle. You are not talking about an insane amount of data if it's 56 Gbit/s. Of course a cac
357.
by Sesse__ 1y ago
It used to be possible back in the days when sequence numbers were easily guessable. (You'd obviously not be able to receive, only send, so you couldn't do TLS, but TLS had hardly been invented at the time.) Now operating systems
358.
by Sesse__ 1y ago
I recognize that you think this is a great injustice towards something, but since the level was moved from .05 to .02 (in 2001), the number of traffic deaths in Norway (of which 64% involved alcohol over the legal limit at the time) has dro
359.
by Sesse__ 1y ago
You're saying this like “having three drinks, waiting a couple of hours and then driving home” is some sort of obviously reasonable (or even desirable) thing to do.
360.
by Sesse__ 1y ago
And typically just fast RAM everywhere instead of caches, so you don't have cache misses. (The flip side is that you typically have very _little_ RAM.)

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