PixelOfDeath

8 ms·

31.
by PixelOfDeath 5y ago
> and the high capacity 3.5 inch models on the market don't use it. Sure they do. WD sold device managed SMR 3.5 disks without telling anyone. And then people noticed because of absolutely terrible raid re-silvering performance. The
32.
by PixelOfDeath 5y ago
QLC also has shitty slow write speed. (Slower then linear writes on spinning rust!) So consumer SSDs now depend on a limited dynamic part of flash being used as SLC to cache writes. Just that this dynamic part mostly gets smaller the fuller
33.
by PixelOfDeath 5y ago
Current consumer QLC devices still do very well in read speed and especially latency. The latency often is better then on older enterprise SSDs. Only device managed SMR is terrible. Host managed SMR is fine for data-hording if the savings i
34.
by PixelOfDeath 5y ago
I would not trust a cheap chinese PCI-E to U.2 connector. And used SAS cards become kind of hot and need active cooling. So why not just directly go for a PCI-E SSD?
35.
by PixelOfDeath 5y ago
I got myself a used pm1725b (PCI-E v3 8x) with 3.2TB for 400€. It hat ~350TB written, and according to Samsung is rated for 3 full device writes per day for 5 years = 17280 TB. So I have some wriggle room left. They use lots of capacitors t
36.
by PixelOfDeath 5y ago
Samsung will give updates for a maximum of 5 years. So all the security holes or missing root certificates (for HTTPS connections) of the integrated browser stagnate after that. Then you have to use a raspberry PI or some other mini compute
37.
by PixelOfDeath 5y ago
With the introduction of QLC consumer SSDs, with worse write endurance and life time but the same price as TLC, I took a look at used enterprise SSDs and never looked back. The only issues is the connectors. You need 8x PCI-E lanes (4x migh
38.
by PixelOfDeath 5y ago
Why not go all they way and let everything run in ring 0? Then Intel can prefetch beyond kernel entry calls again! And we also can see how AMD will performing under the same conditions! With Intels wave of TSX disabling patches going over a
39.
by PixelOfDeath 5y ago
Looking at the world right now, I hope for the best with that gene therapy against sociopathic billionaires.
40.
by PixelOfDeath 5y ago
Then you get them into trying to get their own people into maintainer positions to let the golden stars flow. Maybe also be more hesitant to give out this starts to the "wrong" people from other companies. Not like there already i
41.
by PixelOfDeath 5y ago
Catchinator 22 Traveling back in time to kill humans, indiscriminately from their answers to random questions he asks them beforehand! An early version of this AI can be found in the Microsoft Windows privacy settings.
42.
by PixelOfDeath 5y ago
You basically complain about Vulkan not being portable enough because Apple made their ownTM Vulken-like API instead of actually supporting Vulkan. And some other people made a subset of Vulkan working on top of that. Why don't you com
43.
by PixelOfDeath 5y ago
Enterprise SSDs use capacitor backed dram to buffer writes. Some consumer SSDs do that, too. But with significant smaller amounts of dram. This can intercept all the small writes that you e.g. do for metadata of the filesystem and via mappi
44.
by PixelOfDeath 5y ago
Many SAS expander cards can be chained to support up to 255 devices.
45.
by PixelOfDeath 5y ago
iServer with 64 cores and 128 GiB DDR4 for only $ 399,999.95 iServer with 64 cores and 256 GiB DDR4 for only $ 699,999.95
46.
by PixelOfDeath 5y ago
They hat a 50/50 chance at getting the technical electricity direction right... and the fucked it up!
47.
by PixelOfDeath 5y ago
Until after C++11, ternary was the only way to use "if then" in constexpr functions. So it has slightly more use from a C++ point of view.
48.
by PixelOfDeath 5y ago
https://github.com/Yamahari/struct_array It uses C++20 features and macros. The macros limit it to a POD count of 8.
49.
by PixelOfDeath 5y ago
Don't forget that good cache locality also can cause data being pulled into cache that the prefetcher did know nothing about. I can create you a shitty linked list that fits perfectly in L3, but still has terrible cold cache performanc
50.
by PixelOfDeath 5y ago
There is some, lets call them experimental, C++ libraries for that. But C++ not having static reflection is the main show stopper on that frontier.
51.
by PixelOfDeath 5y ago
That is just to highlight the redundancy!
52.
by PixelOfDeath 5y ago
I wonder if a single bad bit could permanently destroy a whole ~16MiB sector? So SMR drives would need significantly more reserves to compensate for that.
53.
by PixelOfDeath 5y ago
The kind of anime that needs a compressed version, where all the relevant parts of 189* episodes are cut down without all the fillers to 10 minutes max...
54.
by PixelOfDeath 5y ago
> Sure, if you add extra remapping hardware, nonvolatile storage, and eat the performance penalties. Nothing a few fuses can't solve. > Makes sense for massive quantities of crappy cheap flash, not so much for this. Coming from t
55.
by PixelOfDeath 6y ago
Isn't memory the easiest part to remap to use build in redundancies during the factory testing of the chip?
56.
by PixelOfDeath 6y ago
Didn't some Linux maintainers had very clear legal words for NVidia when they tried to make a kernel HAL/ABI?
57.
by PixelOfDeath 6y ago
Pascal was an awesome learning language alone for its compile speed.
58.
by PixelOfDeath 6y ago
The dark side of c is a pathway to many abilities, some considered to be unnatural
59.
by PixelOfDeath 6y ago
My wild guess would be that they hold all data erasure encoded and run regular scrubs. So that any blocks with bit flips would be caught and corrected.
60.
by PixelOfDeath 6y ago
Ask AMD why scaling up to mining demand is a bad idea. A sudden implosion of demand combined with a flooding of the used GPU marked. Better not plan on bringing out any new GPU architectures when your warehouses are still full of the previo

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