Kirby64

101 ms·

1. 1651.▲
   by Kirby64 7y ago

   2.5 GHz, actually. Obviously there's limitations and you have to be careful, but it's not too crazy to think you could use a piece of USB3 cabling to do this. Requires some pretty precise soldering skills though.
2. 1652.▲
   by Kirby64 7y ago

   The Pi4 isn't PCIe Gen 4, though. It's only PCIe Gen 2. Max speed of PCIe Gen 2 is 5GT/s, which equates to the same speed as standard USB3.0/USB3.1 Gen1/whatever its called nowadays.
3. 1653.▲
   by Kirby64 7y ago

   Nope. PCIe lanes are not shared. There are some chips (and a lot of motherboards) that allow (or automatically perform) remapping of lanes, though. That's why if you check a motherboard with SLI/Crossfire, it usually has some s
4. 1654.▲
   by Kirby64 8y ago

   Linearity and drift already covered by the other the other folks... Offset: When something is supposed to read a specific value (usually voltage), what is it actually reading? Most op-amps (configured as buffers) won't actually read 0V
5. 1655.▲
   by Kirby64 8y ago

   EE/CE here: In order if your questions... 1. Assuming you hooked the 5V to the USB 5V and the GND to the USB GND pins, nothing bad would happen. 2. Nothing would get fried 3. Plugged in devices would respond according to how they'