AnIrishDuck

34 ms·

301.
by AnIrishDuck 14y ago
Yeah, this section of the design document made me do a double-take. The problems with this aren't just limited to the impedance mismatch; it also seems that arithmetic will be a ton slower due to lack of dedicated hardware.
302.
by AnIrishDuck 14y ago
I didn't understand your argument at first; after you clarified I believe you are correct (with the corrections mentioned). My comment was intended to fix some flaws in your argument that rendered it incomplete, not incorrect. I believe the
303.
by AnIrishDuck 14y ago
Close, but your example is missing a crucial piece. Specifically, the marginal cost of producing the product. Let's say the MC is 20 cents at the scale produced (Q1). The second group (students) get a MB of let's say 30 cents. They will not
304.
by AnIrishDuck 14y ago
"buyers who pay less than the average" (which I'm assuming means buyers whose reservation price is below the market equilibrium) do not qualify as a deadweight loss. Deadweight loss refers specifically to: a) buyers who cannot buy something
305.
by AnIrishDuck 15y ago
This makes no sense to me. More cores means more processing throughput. Design advances lead to reduced power consumption. Both are happening at the same time, which is the only reason there might be any correlation.
306.
by AnIrishDuck 15y ago
Many CPUs with branch prediction carry a penalty of a least one cycle for mispredicted branches as the fetch stage(s) of the pipeline must be invalidated. From wikipedia: The time that is wasted in case of a branch misprediction is equal to
307.
by AnIrishDuck 15y ago
This has been a subject that caught my interest recently. For those that don't know a lot about SMPC, this library can be used to implement distributed cryptographic applications [1]. In other words, a group of peers that don't trust each o