37ef_ced3

32 ms·

1. 271.▲
   by 37ef_ced3 6y ago

   That's right, SHA-256 of my (unimportant) identity, with salt
2. 272.▲
   by 37ef_ced3 6y ago

   Enough that the data panel of the input tensor fills the thread's share of the L2 cache, and the output tensor is of similar depth So it depends on the cache size, but you can think of it as being about 512 channels in, 512 channels ou
3. 273.▲
   by 37ef_ced3 6y ago

   Thanks. RNN layers later, if I can find the time
4. 274.▲
   by 37ef_ced3 6y ago

   No support for AVX2. AVX-512 is the first really nice (from the programmer's perspective) SIMD instruction set on x86-64 CPUs, and it's significantly different from what came before. AVX-512 is not just a wider version of AVX2 NN-
5. 275.▲
   by 37ef_ced3 6y ago

   No, the convolution generators were written to saturate the hardware For example, under ideal conditions (no out-of-register memory access, no waiting on dependencies) you can sustain 27 single-precision FMADDs per CPU-core per cycle on a p
6. 276.▲
   by 37ef_ced3 6y ago

   NN-512 is an open-source Go program that generates fully AVX-512 vectorized, human-readable, stand-alone C implementations of convolutional neural nets The generated C code is an example of AVX-512 programming using GCC's AVX-512 intri
7. 277.▲
   Show HN: NN-512 – Generate standalone C code for neural nets(nn-512.com)

   111 points by 37ef_ced3 6y ago|28 comments