Primarily they use "silicon on insulator" fabrication, such as silicon on sapphire. Since the feature size on these chips is usually many revs behind the curren

Primarily they use "silicon on insulator" fabrication, such as silicon on sapphire. Since the feature size on these chips is usually many revs behind the current state of the art that results in fairly large transistors on die which helps a bit as well. There are some other techniques used (such as designing to avoid latch-up) but the fabrication technology is the major difference. As much as I hate slide decks as an information source, this one is actually moderately informative: http://meseec.ce.rit.edu/551-projects/fall2013/2-2.pdf http://meseec.ce.rit.edu/551-projects/fall2013/2-2.pdf