3 ms·
Nice! I wrote a 5-stage pipelined RISC MIPS processor in SystemVerilog last semester, in one day, drunk as HELL, but hey, it worked amazingly well. Thank goodne
by nekoeth0 11y ago
Nice! I wrote a 5-stage pipelined RISC MIPS processor in SystemVerilog last semester, in one day, drunk as HELL, but hey, it worked amazingly well. Thank goodness they didn't ask for branch prediction.