Well, its a more than decade old DDS chip. Compare to something only five or so years old like a AD9912 from the same mfgr. Admittedly it costs more and drops

Well, its a more than decade old DDS chip. Compare to something only five or so years old like a AD9912 from the same mfgr. Admittedly it costs more and drops about twice the power, darn near a watt. However, twice the max output frequency, 48 bit tuning word instead of 32 gives somewhat higher precision, 14 bit DAC instead of 10 bit DAC should give much better phase noise performance, a fancy ole PLL refclock input instead of a fixed six-tupler refclock input is more flexible... The "spur-killer" features of the new DDS are kinda cool, you can programmatically predict spurs, more or less, so feed in an intentional signal 180 degrees out of phase and that spur disappears from the output, cool (although it adds complication). The electrical IO capabilities of the new DDS are pretty interesting. Thats all I get in 5 minutes with both datasheets, although I'm sure if I dug in the specific phase noise details of the new chip would likely be way lower. Something instructive to look at WRT complication is the decade old chip has a single 40 bit control "word" aka you squirt 5 bytes at it and call it done. The newer chip has a multiple printed page IO register map with dozens of addresses... programming old DDS was like "undergrad lab class" level of complicated but programming newer DDS is not for faint of heart. In another decade, "one GHz-ish" maybe 64 bit tuning words, 16 bit DAC all sound "believable" for a watt and $25 or so. DDS are cool.