3 ms·

It's fairly common in newer ISAs. For a very modern take, [shameless plug] the Mill CPU instruction encoding talk is very entertaining: http://millcomputing.co

It's fairly common in newer ISAs. For a very modern take, [shameless plug] the Mill CPU instruction encoding talk is very entertaining: http://millcomputing.com/topic/instruction-encoding/ http://millcomputing.com/topic/instruction-encoding/ (Mill team)

pslam 11y ago
It's also very common in older ISAs, especially DSPs. As pointed out elsewhere, it's common in VLIWs (which is generally "older" ISAs). A good example is the Motorola 56K DSP family. Instructions are 24 bit wide (24 bit wide memory!). They come in a few formats, which can be broken down into two major types: complex instruction, or simple instruction plus up to 2 memory moves and address updates. It's basically designed around performing a single-cycle 24x24->56b multiple-accumulate with two memory reads and address increments, with zero loop overhead. The rest of the ISA really, really suffers for it :) But it's impressive when it's doing exactly what it was designed to do! It's a great example of a domain-specific ISA. Also worth noting that in 56K, there is no score-boarding or other dependency tracking to automatically insert pipeline bubbles. That's the job of the hand-writer/assembler/compiler. If you get it wrong, it simply does something undefined. It's "fun" when this happen.
- CountSessine 11y ago
  Yes - this seems to be a common design in DSPs. TI's c64x series is similar - 'instructions' are 32 bits wide and 8 of them are bonded together and issued simultaneously for a mammoth 256 bit instruction 'packet'.
WallWextra 11y ago
What are some examples besides Mill? To be honest, I am totally ignorant of what new ISAs are out there. The only things I can think of are AArch64 and RISC-V (not commercially relevant, but well-publicised) and they are both pretty standard.

3 ms·

It's fairly common in newer ISAs. For a very modern take, [shameless plug] the Mill CPU instruction encoding talk is very entertaining: http://millcomputing.co

by willvarfar 11y ago

pslam 11y ago
It's also very common in older ISAs, especially DSPs. As pointed out elsewhere, it's common in VLIWs (which is generally "older" ISAs). A good example is the Motorola 56K DSP family. Instructions are 24 bit wide (24 bit wide memory!). They come in a few formats, which can be broken down into two major types: complex instruction, or simple instruction plus up to 2 memory moves and address updates. It's basically designed around performing a single-cycle 24x24->56b multiple-accumulate with two memory reads and address increments, with zero loop overhead. The rest of the ISA really, really suffers for it :) But it's impressive when it's doing exactly what it was designed to do! It's a great example of a domain-specific ISA. Also worth noting that in 56K, there is no score-boarding or other dependency tracking to automatically insert pipeline bubbles. That's the job of the hand-writer/assembler/compiler. If you get it wrong, it simply does something undefined. It's "fun" when this happen.
- CountSessine 11y ago
  Yes - this seems to be a common design in DSPs. TI's c64x series is similar - 'instructions' are 32 bits wide and 8 of them are bonded together and issued simultaneously for a mammoth 256 bit instruction 'packet'.
WallWextra 11y ago
What are some examples besides Mill? To be honest, I am totally ignorant of what new ISAs are out there. The only things I can think of are AArch64 and RISC-V (not commercially relevant, but well-publicised) and they are both pretty standard.