I wrote this after the discussion on https://news.ycombinator.com/item?id=9935597 https://news.ycombinator.com/item?id=9935597. Feel free to ask any Verilog qu

I wrote this after the discussion on https://news.ycombinator.com/item?id=9935597 https://news.ycombinator.com/item?id=9935597. Feel free to ask any Verilog question or point any rule I missed (I'm sure there are many).