Here is some information on the speed of MyHDL, http://www.myhdl.org/documentation/performance.html http://www.myhdl.org/documentation/performance.html. Conver

Here is some information on the speed of MyHDL, http://www.myhdl.org/documentation/performance.html http://www.myhdl.org/documentation/performance.html. Converting to yet another format can be a pain and potentially dangerous, if you are creating a commercial ASIC you need to guarantee each of these formats/representations are equivalent, if there is a discrepancy between the generated C++ and generated Verilog for implementation - oh boy.