3 ms·
Excellent point. I believe that the ADC samples at 28.8 Msps and then decimates to the rate requested by the computer (max ~3.2 Msps). So theoretically it cou
by olympus 11y ago
Excellent point. I believe that the ADC samples at 28.8 Msps and then decimates to the rate requested by the computer (max ~3.2 Msps). So theoretically it could be doing ~3 bits better, if everything was implemented properly and those extra bits were delivered across the USB to the computer. I think the samples delivered to the computer are still only 8 bits so the ~48 dB theoretical limit to the dynamic range remains.
CamperBob you sound like you know what you're talking about and I'm mostly self taught in this area so if I'm wrong please let me know.
- CamperBob2 11y agoSame here, I (try to) spend most of my time out of my depth. :) It sounds like the bandwidth of the 137 MHz satellite signal is in the 36 kHz vicinity, going by the article. So one possible strategy would downconvert 137 MHz to somewhere in the first Nyquist zone of the ~30 MSPS ADC (i.e., below about 15 MHz). The ASIC picks up 3 more bits of process gain by decimating to 3 MSPS, then the host CPU could pick up about 5 more bits by further decimation to about 100 kSPS. The 36 kHz signal would then have a dynamic range approaching that of a 16-bit ADC, which is quite adequate for most purposes. Of course, IMD artifacts and other spurious tonal responses due to the cheap RF front end don't experience any such improvement, but you sure can't complain for $20.