4 ms·

Still , Cx - lang is having a real hard time to find customers. So what's missing ?

• nickpsecurity 11y ago
  That's part of what I'm trying to find out. To be fair, most open-source, high-level synthesis tools don't have a lot of customers. Even Chisel doesn't have near as many users as its successes deserve. That's common for ASIC or FPGA tools that aren't the big name. For now, my preliminary answer is that people: (a) just use Altera and Xilinx HLS tools for FPGA because they're cheap and work well with their products; (b) use HLS tools from big three EDA companies on ASIC design; (c) straight up do HDL (majority probably) for ASIC as experienced HW engineers are used to doing anyway and use good RTL synthesis. Against the competition, there's no comparison of free/open synthesis tools except in price and subversion risk. Those are my reasons for investigating them, though, so I continue to get feedback on what I find. Note: Not sure of your HW expertise. If you're not a HW person, I'll note that anything synthesized for ASIC's needs to have a rock-solid method because mistakes are expensive. Even older processes still cost hundreds of thousands for the masks that print an instance of a design. Production engineers are hesitant to use unproven technology when $$$ are on the line.
  • MootWoop 11y ago
    Matthieu, co-founder of Synflow here. Maybe I could help? Don't hesitate to send me an email!
    • nickpsecurity 11y ago
      I probably will soon since you took the time to show up. :) I think what I'll do is form a list of questions to assess the nature and capabilities of your method. These will represent what a lot of different kinds of people would ask. Then, your answers might get packaged up in FAQ's, blog posts, whatever that clarify things for more people than just me. How's that sound?
      • MootWoop 11y ago
        Sounds great! I'll do my best to answer all questions :-) My email is matthieu.wipliez@synflow.com