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Chisel: Constructing Hardware in a Scala Embedded Language
- minthd 11y agoThey claim this language is highly parameterized. I wonder how much. For example can you design a generic processor in such a way that everything will be parameterized?
- rjsw 11y agoThey use this language for RISC-V, if you look at the sources you can see the kind of things that can be parameterized.
- cmrx64 11y agoI've been playing with this for the past few weeks. It's a lot of fun compared to Verilog or VHDL. The implementation is still young, though, and it's pretty easy to trigger an undecipherable crash. But I haven't had anything miscompile yet.
- ci5er 11y agoI'm trying to get the Amulet1 (Async/unclocked ARM from Manchester, back in the day) working as a test project. This, of course, requires Muller C-gate stuff. I'm having a bit of trouble getting it all to work out. Have you seen any obvious techniques/methods for unclocked circuits that I am probably looking right past?
- bra-ket 11y agoit's used by Rex: http://www.theplatform.net/2015/07/22/supercomputer-chip-startup-scores-funding-darpa-contract/ http://www.theplatform.net/2015/07/22/supercomputer-chip-sta...
- trsohmers 11y agoHey, CEO of REX here... would be happy to answer questions. P.S. We're hiring Chisel developers! If you don't know chisel, but want to learn and have RTL experience, we'd love to have you learn on the job! Check out our website: http://rexcomputing.com http://rexcomputing.com
- Skooma 11y agoWhat differentiates your company's Neo Chip vs Adapteva's Epiphany co-processor?
- trsohmers 11y agoA number of things... The first thing is that Neo is not a coprocessor, it is a fully independent many core processor. To quickly go over the basics: 1. Neo has a 64 bit core, and conforms the IEEE 754-2008 Floating Point standard... Epiphany is 32 bit, and is not fully IEEE compliant (along with only being capable of single precision FP). 2. The existing Epiphany chips cap out at 32KB of local memory per core (with the Epiphany IV having a total of 2MB of on chip memory), while the planned Neo chip will have 128KB of local memory per core (32MB of on chip memory). 3. Epiphany is limited to using it's 4 eLink (based on ARM's AXI interface) connectors to access the outside world, and would typically be connected to either other Epiphany chips or to its host processor. Each eLink port only supports 1.6GB/s bidirectional traffic, giving a total of 6.4GB/s of aggregate chip bandwidth. For Neo, we have developed a new 96GB/s (bidirectional, 48GB/s each way) interface with either 3 or 4 interfaces per chip, giving an aggregate chip-to-chip bandwidth of 288-384GB/s. 4. Neo can directly address DRAM attached to it, instead of having to go through a host processor. 5. Neo is a Quad issue VLIW core (capable of a 64 bit ALU op, 1 64 bit FPU op/2 32 bit FPU ops, and 2 load/store ops every cycle) compared to Epiphany's standard superscalar core (Capable of 1 32 bit ALU op, 1 32 bit FPU op, and 1 load/store op per cycle). All of this adds up to actually being a commercially viable (for industry, not hobbyists) processor. Above all, memory bandwidth has been what kills Epiphany and completely prevents it from reaching their advertised performance.
- stephenmm 11y agoChisel is potentially a revolution in hardware design and I am following it intently but I have not heard of anyone creating an actual chip from a standard fab as of yet. I am trying to make an argument for trying this at my work but I think until we get some more feedback from people in industry it may be too risky of an endeavour. It would be great if you would be willing to share your experiences or know of some papers that would help me build an argument for trying it out.
- Skooma 11y agoIn my opinion, Chisel feels like "lets write Verilog with Scala syntax." I personally see MyHDL as a better approach as you can leverage existing libraries for generating code (i.e. use scipy to generate the coefficients for your FIR filter). One plus is Chisel generates C++ code for testing your design which is a huge speed increase versus simulating Verilog.
- trsohmers 11y agoThe biggest problem with MyHDL in my opinion (As someone using Chisel to make a commercial processor) is its (non existent) "real" simulation capabilities. If something is not cycle accurate (the way that Chisel's C++ simulator is), you can not really be positive of anything...and you don't want to get to physical design and find out you can't meet timing.
- gluggymug 11y agoYou saying MyHDL is not cycle accurate? Could you give a citation for that?
- trsohmers 11y agoCheck out the bottom: http://www.myhdl.org/start/whatitisnot.html http://www.myhdl.org/start/whatitisnot.html I should say that in generating Verilog or VHDL from MyHDL, you can do proper simulations with that... but Chisel's C++ simulator is significantly faster than a Verilog simulator, while still being cycle accurate.
- gluggymug 11y agoOkay this is getting weird. I just read your link so this is all from my first impressions. MyHDL is talking about co-simulation on the gate-level netlist. They do not recommend it. However they say MyHDL can do co-simulation on Verilog RTL. That will be cycle accurate I believe. As I understand it Chisel can't even do co simulation at all. Am I incorrect? Essentially once you translate your Chisel design to verilog you basically can't reuse your verification environment for the RTL simulation or the gate-level. How are you going to check timing if you wrote all your tests in Chisel? So Chisel seems worse than MyHDL but neither can support verifying a gate-level sim so you are somewhat screwed either way. It's just a matter of how badly screwed you are. That's kinda the problem with all these tools I believe. A while ago someone posted about Clash. Same issue.
- nickpsecurity 11y agoChisel is a nice toolkit that proved itself in the Rocket processor. One of the more unusual uses of it was Chisel-Q for quantum computing: http://www.cs.berkeley.edu/~kubitron/papers/qarc/pdf/Chisel-q.pdf http://www.cs.berkeley.edu/~kubitron/papers/qarc/pdf/Chisel-... Chisel is pretty well-known in academic, hardware community. So, here's a few that you might have not heard of. Caisson - language-based security meets HDL http://www.cs.ucsb.edu/~chong/papers/109-Caisson-pldi.pdf http://www.cs.ucsb.edu/~chong/papers/109-Caisson-pldi.pdf SHard - a scheme to hardware compiler http://scheme2006.cs.uchicago.edu/05-saint-mleux.pdf http://scheme2006.cs.uchicago.edu/05-saint-mleux.pdf Cx-Lang - A statically-typed, c-like, HLL for hardware http://cx-lang.org/ http://cx-lang.org/ Note: I'd love for some people familiar with ASIC or FPGA design to check out Cx-Lang to see if it's good for beginners getting results on FPGA's. The I.P. they sell is so cheap that it's either (a) crap or (b) the result of a productive, synthesis tool (Cx). Just like to know if it's a decent HLS tool compared to FPGA or EDA company offerings. Additional advantage that it's open so it can be reviewed for subversion if one is willing to invest the effort.
- gluggymug 11y agoJust took at look at the cx-lang website. I think it may be too weird for a beginner looking for results. I've been in ASIC & FPGA engineering for 15+ years. The design flow I think they use is more like writing a program that gets translated into hardware. Very different from the regular methodology. Sounds great but there's a big leap between that and getting your FPGA working. For a beginner, it's too much to take on. I think maybe Chisel and those others would be easier.
- nickpsecurity 11y agoYeah, I was actually hoping it was a high-level synthesis tool. I appreciate your review on the ease-of-use aspect.
- gluggymug 11y agoI think it is a high level synthesis tool like a SystemC etc. My concern for a beginner would be how to get your high level design integrated into the FPGA. For a beginner, there are a lot of what-ifs that they are probably going to stumble on.