I keep pointing people to the page I started a while back: Verilog for Software programmers (https://en.wikibooks.org/wiki/Programmable_Logic/Verilog_for_Softwa

I keep pointing people to the page I started a while back: Verilog for Software programmers (https://en.wikibooks.org/wiki/Programmable_Logic/Verilog_for_Software_Programmers https://en.wikibooks.org/wiki/Programmable_Logic/Verilog_for...) Maybe it's time for me to add another one: good Verilog RTL coding style, or basic RTL rules for Verilog... Based on the kinds of mistakes I see online, it would be easy to cover initial blocks, multiple assignments, etc. EDIT: just started https://en.wikibooks.org/wiki/Programmable_Logic/Verilog_RTL_Coding_Guidelines https://en.wikibooks.org/wiki/Programmable_Logic/Verilog_RTL... . For now, just contains placeholders for the items I want to cover, but feel free to add to the list, that's the whole point of a wiki.