>We already have software runtimes (various Javascript VMs, .NET, the JVM and its offshoots, etc) that can optimize code at runtime based on the hardware that's

>We already have software runtimes (various Javascript VMs, .NET, the JVM and its offshoots, etc) that can optimize code at runtime based on the hardware that's present, hotspots in the code, etc. Are you a hardware guy? :) Thanks for elaborating. I had no idea how you went from "memory latency is a problem, that's why we have L_n caches" to "memory latency is a problem, we'll probably solve it ... (with cache)." This helps. The biggest problem I see with integrating FPGAs into designs (HW) is educational. An on-die accessory FPGA doesn't amount to much if it doesn't get used. It's coming though. One way or another we're going to see more flexible HW. Taking advantage of it won't be something we're used to.