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FPGA eats a ton of power. You won't see it anything consumer. It is already used in Server/Pro applications.

by bravo22 11y ago

nickpsecurity 11y ago
There's plenty of low watt FPGA's, even mW's. The Cyclones, etc get 4,000+MIPS in under 2 watts. Microsemi already does FPGA's that run milliwatts with enough slices to support 5-6 accelerators concurrently. As the example below shows, you can have two Stratix's, a CPU, and a whole board's worth of stuff using only 45watts. Merely adding a few layers to an SOC at Intel's new nodes should use way less power than all that. I'm sure Altera's, with Intel's help, will be pretty sweet given they're mainly targeting datacenter use where performance-per-watt is key criteria. Still, worst case, I'll gladly add 45watts to a gaming/workstation rig... which probably already has a several hundred watt power supply... in exchange for Stratix IV's 500,000+ LE's, 20Mbit SRAM, 20+ 8.4Gbps transceivers, and more direct CPU-to-FPGA link. You have no idea what I can do with that amount of logic and interface speed. A whole OpenSPARC T1 setup only takes 173,000 LE's. Most extensions to make highly secure processors take up a small fraction of that. So many possibilities and so little time/money. :) http://www.theplatform.net/2015/05/28/the-other-cray-launches-cpu-fpga-hybrids/ http://www.theplatform.net/2015/05/28/the-other-cray-launche...
- techdragon 11y ago
  I wonder how many people forget (or never learned) that unlike the X86, MIPS, ALPHA, and ARM architectures, SPARC is an open standard and anyone can make a 100% ISA compatible SPARC CPU... SPARC deserves much more love from the open hardware community than I see it receiving.
  - nickpsecurity 11y ago
    Upvote for you seeing as you're educated on the subject! :) I've been telling these secure CPU teams to use it for a while. A few have but most didn't. SAFE went with discontinued, but still I.P., Alpha. (rolls eyes) Shit, the Oracle SPARC T1 & T2 processors were first real CPU's to go open source! Here was my recommendation for open hardware crowd in another HN thread: "The RISC-V activity is very interesting. I particularly love that they did a 1.4GHz core on 48nm SOI and are working on 28nm level. This knocks out some of the early, hard work of getting competitive hardware at an advanced process node. I'd like to see two things in this work: microprogrammed variant with an assembly or HLL to microcode compiler; tagged variant like SAFE/CHERI processors with IO/MMU that seemlessly adds & removes tags during DMA. That would be way better for security-critical applications than most of what's out there. Multi-core would help, too. Meanwhile, Gaisler's SPARC cores are commercial, open-source, customizable, support up to 4 cores in Leon4, integrated with most necessary I.P., and can leverage the SPARC ecosystem. Anyone trying to do an open processor can get quite the head-start with that. A few academic and commercial works are already using it. Plus, the SPARC architecture is open as such that you only pay around $100 for the right to use its name. So, Gaisler's SPARC cores with eASIC's Nextreme seems to be the best way to rapidly get something going. The long-term bet is RISC-V and they could do well copying Gaisler's easy customization strategy. Might be doing that already with their CPU generator, etc: I just read the Rocket paper so far. The solutions built with one can include a way to transition to the other over time."
- bravo22 11y ago
  You are way, way off on your calculations. The Cyclone IV "MIPS" you are talking about comes from the built-in ARM cores so you're comparing ASIC to ASIC here. An FPGA vs ASIC, FPGA will lose every time. It is a simple matter of architecture. You have more crap to make the FPGA an FPGA, whereas in ASIC you have optimized gates. So it doesn't make sense for Intel to ship FPGA + CPU for consumer/mobile. Period. You burn more power and no one needs it. FPGAs are also more expensive because they take a ton of silicon space for a comparable function. FPGA SoCs like Xilinx Zynq or Altera's offerings are widely used but for specific applications, none of it really consumer/mobile/desktop. Stratix IV FPGAs that you are talking about are many thousands of dollars, each. You can get them today and hang them off your PCIe bus and do whatever you want with them. There is nothing stopping you. Putting it on the same die as a CPU won't buy you anything you don't get today -- except a lot of more heat you have to get rid of. I don't think electrical engineering works the way you think it does. For reference: I've designed ASICs and have done a lot of FPGA work in the past 10 years.

FPGA eats a ton of power. You won't see it anything consumer. It is already used in Server/Pro applications.

by bravo22 11y ago

FPGA eats a ton of power. You won't see it anything consumer. It is already used in Server/Pro applications.

There's plenty of low watt FPGA's, even mW's. The Cyclones, etc get 4,000+MIPS in under 2 watts. Microsemi already does FPGA's that run milliwatts with enough slices to support 5-6 accelerators concurrently. As the example below shows, you can have two Stratix's, a CPU, and a whole board's worth of stuff using only 45watts. Merely adding a few layers to an SOC at Intel's new nodes should use way less power than all that. I'm sure Altera's, with Intel's help, will be pretty sweet given they're mainly targeting datacenter use where performance-per-watt is key criteria. Still, worst case, I'll gladly add 45watts to a gaming/workstation rig... which probably already has a several hundred watt power supply... in exchange for Stratix IV's 500,000+ LE's, 20Mbit SRAM, 20+ 8.4Gbps transceivers, and more direct CPU-to-FPGA link. You have no idea what I can do with that amount of logic and interface speed. A whole OpenSPARC T1 setup only takes 173,000 LE's. Most extensions to make highly secure processors take up a small fraction of that. So many possibilities and so little time/money. :) http://www.theplatform.net/2015/05/28/the-other-cray-launches-cpu-fpga-hybrids/ http://www.theplatform.net/2015/05/28/the-other-cray-launche...

techdragon 11y ago
I wonder how many people forget (or never learned) that unlike the X86, MIPS, ALPHA, and ARM architectures, SPARC is an open standard and anyone can make a 100% ISA compatible SPARC CPU... SPARC deserves much more love from the open hardware community than I see it receiving.
- nickpsecurity 11y ago
  Upvote for you seeing as you're educated on the subject! :) I've been telling these secure CPU teams to use it for a while. A few have but most didn't. SAFE went with discontinued, but still I.P., Alpha. (rolls eyes) Shit, the Oracle SPARC T1 & T2 processors were first real CPU's to go open source! Here was my recommendation for open hardware crowd in another HN thread: "The RISC-V activity is very interesting. I particularly love that they did a 1.4GHz core on 48nm SOI and are working on 28nm level. This knocks out some of the early, hard work of getting competitive hardware at an advanced process node. I'd like to see two things in this work: microprogrammed variant with an assembly or HLL to microcode compiler; tagged variant like SAFE/CHERI processors with IO/MMU that seemlessly adds & removes tags during DMA. That would be way better for security-critical applications than most of what's out there. Multi-core would help, too. Meanwhile, Gaisler's SPARC cores are commercial, open-source, customizable, support up to 4 cores in Leon4, integrated with most necessary I.P., and can leverage the SPARC ecosystem. Anyone trying to do an open processor can get quite the head-start with that. A few academic and commercial works are already using it. Plus, the SPARC architecture is open as such that you only pay around $100 for the right to use its name. So, Gaisler's SPARC cores with eASIC's Nextreme seems to be the best way to rapidly get something going. The long-term bet is RISC-V and they could do well copying Gaisler's easy customization strategy. Might be doing that already with their CPU generator, etc: I just read the Rocket paper so far. The solutions built with one can include a way to transition to the other over time."
bravo22 11y ago
You are way, way off on your calculations. The Cyclone IV "MIPS" you are talking about comes from the built-in ARM cores so you're comparing ASIC to ASIC here. An FPGA vs ASIC, FPGA will lose every time. It is a simple matter of architecture. You have more crap to make the FPGA an FPGA, whereas in ASIC you have optimized gates. So it doesn't make sense for Intel to ship FPGA + CPU for consumer/mobile. Period. You burn more power and no one needs it. FPGAs are also more expensive because they take a ton of silicon space for a comparable function. FPGA SoCs like Xilinx Zynq or Altera's offerings are widely used but for specific applications, none of it really consumer/mobile/desktop. Stratix IV FPGAs that you are talking about are many thousands of dollars, each. You can get them today and hang them off your PCIe bus and do whatever you want with them. There is nothing stopping you. Putting it on the same die as a CPU won't buy you anything you don't get today -- except a lot of more heat you have to get rid of. I don't think electrical engineering works the way you think it does. For reference: I've designed ASICs and have done a lot of FPGA work in the past 10 years.