4 ms·
look back and laugh at how long we were able to just shrink transistors within the 1 plane, totally ignoring all depth? Remember, moore's law is about transisto
by logicallee 11y ago
look back and laugh at how long we were able to just shrink transistors within the 1 plane, totally ignoring all depth? Remember, moore's law is about transistor count per square inch. I'm kind of shocked we don't use 3D chips, though I understand heat is an issue.
- Retric 11y agoChips are 3d, Intel for example uses 13 layers. There are massive heat and cost issues when adding layers, but flatter chips have latency issues. Stacking chips is also common in cellphones and other low power designs.
- deleted 11y ago[deleted]
- nhaehnle 11y agoThe 13 layers Retric was referring to are not layers of transistors, but layers of wiring. All chips currently manufactured only have a single layer of transistors. Above this single layer of transistors are many layers for wires which are alternatingly used for wires mostly in X- and mostly in Y-direction.
- logicallee 11y agoThat's what I had thought (and reflected in my brief comment - "transistors within the 1 plane") - it seemed they corrected me, to my surprise. Thanks.
- pjc50 11y agoManufacturing process is the main issue. Too many layers and it's impossible to keep flat enough to build the next layer on. Chip-on-chip is however becoming widespread, keeping your DRAM nice and close.
- kllrnohj 11y agoAMD's new desktop GPUs use 4 tall stacked memory modules. Stacked chips are definitely a thing. When this makes its way to compute modules remains to be seen, though.