8 ms·
If Moores law ends with 14nm, I wonder what we'll be doing 10 years from now.
by narrator 11y ago
If Moores law ends with 14nm, I wonder what we'll be doing 10 years from now.
- fdej 11y agoI guess we'll be removing cruft from the web.
- minthd 11y agoMaybe(in 10-20 years) We'll build analog imitations of the brain , with similar density and high power efficiency. Or maybe we'll build other types of compute machines using analog electronics. Maybe we'll replace digital multiplies with pseudo digital multipliers that use analog computation the background, and with other forms of non-exact computation. Or We'll use photonics to analogically compute FFT's to multiply matrixes. Or maybe we'll finally seriously and successfully invest in optical digital computing. Or we'll crack quantum computing.
- pjc50 11y agoAnalog and "non-exact" computation is not something that sounds very useful. The only reason we've been able to minimise so much is the tremendous noise rejection of binary systems. Besides, modern computers are spending most of their time on actions of marginal or negative utility, mostly data-bureaucratic rather than computational.
- minthd 11y agoNon-exact computation is useful for some stuff: machine vision, deep-learning, and probably other types of machines learning. Those have a wide variety of uses and they demand lots of compute. Also in places where performance is critical and money is spent on optimization, isn't lots of this bureaucracy removed ?
- kardos 11y ago> Analog and "non-exact" computation is not something that sounds very useful. Floating point operations are non exact in general. Physics simulations work at various degrees of approximation. Non exact computations would be useful as long as we can quantify the "non-exactness".
- roghummal 11y ago>Maybe(in 10-20 years) I've seen 20 years of progress. Yeah... not to discourage you; Keep on shooting for the stars.
- Quequau 11y agoThere was an excellent presentation at HotChips 2013, given by Robert Colwell from DARPA on that topic.
- solomatov 11y agoIt's available on youtube https://www.youtube.com/watch?v=JpgV6rCn5-g https://www.youtube.com/watch?v=JpgV6rCn5-g
- ghaff 11y agoThat's an interesting presentation in that it outlines a lot of the directions--including rather novel ones--that processor technology could potentially be taken. He also emphasized more system-level thinking. At the same time, he also emphasizes just what an amazing technology CMOS has been and how that's made it such an important part of the computer revolution of the last 30 years. So, no, it's not like progress will stop but without the tailwind that CMOS scaling supplied, I expect the rate of advance in a lot of areas will slow down. (As, indeed, we're seeing on desktops and laptops today even if there are also other dynamics in play.)
- Keyframe 11y agoAdd more chips / cores!
- logicallee 11y agolook back and laugh at how long we were able to just shrink transistors within the 1 plane, totally ignoring all depth? Remember, moore's law is about transistor count per square inch. I'm kind of shocked we don't use 3D chips, though I understand heat is an issue.
- Retric 11y agoChips are 3d, Intel for example uses 13 layers. There are massive heat and cost issues when adding layers, but flatter chips have latency issues. Stacking chips is also common in cellphones and other low power designs.
- deleted 11y ago[deleted]
- nhaehnle 11y agoThe 13 layers Retric was referring to are not layers of transistors, but layers of wiring. All chips currently manufactured only have a single layer of transistors. Above this single layer of transistors are many layers for wires which are alternatingly used for wires mostly in X- and mostly in Y-direction.
- logicallee 11y agoThat's what I had thought (and reflected in my brief comment - "transistors within the 1 plane") - it seemed they corrected me, to my surprise. Thanks.
- pjc50 11y agoManufacturing process is the main issue. Too many layers and it's impossible to keep flat enough to build the next layer on. Chip-on-chip is however becoming widespread, keeping your DRAM nice and close.
- kllrnohj 11y agoAMD's new desktop GPUs use 4 tall stacked memory modules. Stacked chips are definitely a thing. When this makes its way to compute modules remains to be seen, though.
- noir_lord 11y agoUsing languages with low(er) complexity parallelism, optimising existing code as much as possible and (possibly) writing code for FPGA's (modern processors are pretty good at doing lots of things reasonably well but workload tuned FPGA's kill them and 10 years of FPGA research after a boatload of cash could be interesting). Also if we are bottoming out on Silicon then investment into other technologies should pick up, Graphene and the like. It should be exciting, Intel has had a lock on the desktop processor market for over 30 years (by volume if not technical excellence at some points).
- craigjb 11y agoThere is also a lot of space between general purpose CPU and completely blank-slate FPGAs. GPUs are essential very wide data word processors (one instruction but a large data vector). And, there are also configurable pipeline processors that consist of multiple ALUs (can be vector data) with reconfigurable connections between them. So rather than eat the overhead of generic bit LUTs in an FPGA, you reconfigure the interconnect in a fabric of ALUs. The fabric can contain specialized ALUs (or execution units), and varying densities depending on typical usage. This avoids a the technology mapping and place & route of FPGA design. Translating a description of hardware (HDL) into actual lookup table data is a massive compute problem for large modern FPGAs. However, if we collapse the routing to just data buses between compute units, the problem can be solved in real-time. This way, a compute pipeline could be reorganized by an application at run-time without using a full-fledged hardware description language with all kinds of very low-level constructs. Higher-level language compilers already exist for this kind of architecture in academia. EDIT: The sea of ALUs can also contain memories, FIFOs, and other block elements. However, they would all operate on the same word size to reduce the routing problem and allow maximum density implementation. In fact, this is the essence of how micro-coded instructions in a modern CPU work anyway--instruction 'scheduling' is basically figuring out how to route data transfers in a sea of execution units. The article "Fundamental Underpinnings of Reconfigurable Computing Architectures" in the March 2015 Proceedings of the IEEE contains a wonderful introduction to all these concepts.
- white-flame 11y ago
- mrb 11y agoIt is very obvious what we will be doing, and this has been discussed many times: add more metal layers. Intel processors only have a dozen layers which stack up to less than ~1 um. The numbers of transistors/layers could in theory be increased by 1000x if the layers were stacked ~1 mm high. How to do this with lithographic processes is an open question, but it is absolutely doable in theory. No physical limits prevent us from doing that.
- knd775 11y agoHeat would be a massive issue with more layers, right?
- chucky_z 11y agoFrom a purely seat-of-my-pants-im-trying-to-remember-college point of view, I believe the heat is caused far more by pumping tons of electricity, rather than physical size/layout. A big problem (and also probably why they're so thin) is that at a certain size latency becomes a huge issue. This is where clock speed increases come into play (electrons move faster) along with die decreases (electrons can travel shorter distances). If you can run 100mph, but you have to run 200 miles vs. someone who can walk 1mph, but only has to walk 10 feet... I wish I had some more concrete examples but I can't come find anything off the top of my head.
- t0mbstone 11y agoHeat is caused by resistance when the electricity moves through the metal. The more metal the electricity is flowing through, the more material there is incur resistance and generate heat, correct? If so, then more layers = more heat.
- ars 11y ago> Heat is caused by resistance when the electricity moves through the metal. Sort of. But if you reduce resistance you increase heat since more current will flow. On the other hand, if you increase resistance AND also keep the current the same then you'll get more heat. But! to keep that current constant you must increase the voltage. So it's not so simple as "resistance = heat". > The more metal the electricity is flowing through, the more material there is incur resistance Depends on if the metal is in parallel or series. If in parallel, then the more metal the lower the resistance, if in series then higher resistance. > If so, then more layers = more heat. Right result, wrong method of getting there. More layers (which would be in parallel) would be less resistance. But less resistance means more current flow (since they'll keep the voltage the same), and more current flow means more heat.
- JohnBooty 11y agoAs others have noted, workload-specific FPGAs are very promising. Another big bottleneck is memory latency. For each cache miss, a modern CPU spends hundreds or even thousands of clock cycles doing nothing. A majority of the transistors in your CPU are dedicated to mitigating this in one way or another - the L1/L2/L3 caches, transistors dedicated to branch prediction, etc. I don't know what the outlook for improving the memory latency situation is. It's probably going to involve gobs of on-chip embedded RAM, which is expensive.
- roghummal 11y agoWhat good is an FPGA if it isn't 'workload-specific'? That's what they do. That workload might be a processor, it might be an interface, ... you get it. Workload-specific FPGAs are here, now. They're not 'promising' because they're doing exactly what they were made to do! >I don't know what the outlook for improving the memory latency situation is. It's probably going to involve gobs of on-chip embedded RAM, which is expensive. They already have a name for that and you already named it. It's called cache ;)
- JohnBooty 11y agoWorkload-specific FPGAs are here, now. They're not 'promising' because they're doing exactly what they were made to do! Right. I was thinking in terms of them being more integrated into hardware and software toolchains. We already have software runtimes (various Javascript VMs, .NET, the JVM and its offshoots, etc) that can optimize code at runtime based on the hardware that's present, hotspots in the code, etc. Now imagine if FPGAs were integrated into your typical laptop/desktop logic board. Now imagine those software runtimes we talked about above could optimize your hardware at runtime as well. Or maybe it wouldn't be transparent; maybe FPGA hardware would be targetable like GPU hardware is today. Anyway, there's a lot of things that could happen there... They already have a name for that and you already named it. It's called cache ;) I should have said "embedded DRAM" instead of "embedded RAM." eDRAM is different from your typical CPU cache. Your CPU cache is almost always SRAM. But SRAM takes up 3x as much die space as an equivalent amount of eDRAM. Of course... some processors like IBM's POWER chips use eDRAM as L3 cache so the lines are blurred a little. A lot of game consoles use embedded DRAM for stuff like graphics processing. On the XBox One I believe it's used as a framebuffer.
- SEJeff 11y agoWriting CRUD apps, the same thing that we've always been doing overall as an industry :)
- the8472 11y agoMoore's law ending just means progress will slow, not cease. But in addition to that there are other things we could optimize. For example a lot of transistor budget is spent on caches and very clever out of order execution. If memory bandwidth could be increased to the point where those deep out of order pipelines aren't needed anymore to mask memory latency then maybe we could utilize the chip area better. SRAM used for caches also eats a tremendous amount of space and power due to its 6T, always-powered design. Imagine MRAM (1T, non-volatile), manufactured in the same process node as the CPU itself, stacked right onto the CPU and/or connected with light-based transports. Since MRAM doesn't need to be powered when it's idle it would also allow for rapid power-switching, thus giving the chip designers more thermal headroom. Another thing: Remember how chips used to shrink and increase in clock speed? Well, the gigahertz race has been over for a while. But if they use the longer process-nodes to introduce new technologies (different semiconductors, carbon nanotube conductors, ...) then there might be new room to push a few extra GHz. Progress will certainly slow and at some point it'll require radical re-designs, but there's still a lot of room for improvements.
- jjoonathan 11y ago> SRAM used for caches also eats a tremendous amount of space and power due to its 6T, always-powered design. What gets in the way of using SRAM for main memory? I've always been told that it's the space multiplier (6T vs 1T+1C) but that never seemed terribly convincing because DRAM is cheap enough (and has been cheap enough for a while) that it would make sense to pay a 3x-5x premium to avoid page open/close latency even in the high-end consumer market. Heck, many consumer devices are already 2-4x overprovisioned with DRAM just in case someone doesn't like closing chrome tabs (or whatever). By process of elimination I tend to suspect it's the power draw, but it seems odd that power from leakage current on inactive SRAM gates would dramatically exceed that of DRAM's active refreshes. What gives?
- bsder 11y agoSimply put: nobody cares for big microprocessors. There is so little performance gain from switching from DRAM to SRAM that it just doesn't really matter. Caches are very good at hiding accesses to memory, and, if you need to hit a flash drive/hard disk, you are hosed anyway. Where people care a lot is in embedded microprocessors. SRAM is very scarce, and it's very definitely about area and power as DRAM basically isn't used. The problem is that you can put almost 10x more flash in the same area as SRAM (and I'm being generous--it's probably more like 20x now) and memory (flash and SRAM) is more than 50% of the die area on a modern microcontroller. Basically, every modern microcontroller ships with the maximum amount of SRAM that it is economically feasible to make. In addition, for "modern" technology nodes, SRAM cost is going up. Moore's Law broke back at the 28nm node. http://electroiq.com/blog/2014/02/the-most-expensive-sram-in-the-world-2-0/ http://electroiq.com/blog/2014/02/the-most-expensive-sram-in...
- roghummal 11y agoIntel's 7nm? Anyone?