3 ms·

The best flash FPGA that would fit your goal is probably on 65nm. if that's the case , you're better of verifying on FPGA,selling low volumes on 90nm easic -whi

by minthd 11y ago

The best flash FPGA that would fit your goal is probably on 65nm. if that's the case , you're better of verifying on FPGA,selling low volumes on 90nm easic -which will be far more efficient than 65 nm fpga ,expect very expensive prices at low volume , but than you could scale. BTW if security is what you sell, isn't any option to do it at the software only level and reach bulletproof security?

nickpsecurity 11y ago
I used to do that with separation kernels, security through diversity, and so on. My framework (below) I eventually published for free after Snowden leaks because people weren't keeping up with attackers. http://pastebin.com/y3PufJ0V http://pastebin.com/y3PufJ0V Thing is, though, that the hardware kept getting in the way. I discovered too slowly that the problem, as Snow said, was the hardware inherently made safe or secure computing difficult. So, my counterpoint to Dan Geer (below) pointed that out, gave many examples, and showed it must be the first step. So, we need hardware like Burroughs, System/38, SAFE (crash-safe.org), or Cambrige's CHERI that makes our job inherently easy instead of FUBAR. https://www.schneier.com/blog/archives/2014/04/dan_geer_on_hea.html#c5598568 https://www.schneier.com/blog/archives/2014/04/dan_geer_on_h... FPGA's might be modified by clever software attack along with being slow and expensive. ASIC's with right logic might be immune to software attack and fast but are EXPENSIVE. So, I was exploring S-ASIC option for non-modifiable, cheaper NRE than ASIC, and faster/cheaper than FPGA (maybe). I was going to do anti-fuse if I had to do FPGA's. Not sure what their cost or tooling is like vs typical Altera or Xilinx FPGA's. Anyway, that's what I was aiming at. Appreciate your tip. Hmm, Opterons and PowerPC G5's were done at 90nm albeit custom. Can probably squeeze quite a bit more performance out of that easic than I thought. Could always go old school and do 4-way SMP box. :)

by minthd 11y ago

nickpsecurity 11y ago

I used to do that with separation kernels, security through diversity, and so on. My framework (below) I eventually published for free after Snowden leaks because people weren't keeping up with attackers. http://pastebin.com/y3PufJ0V http://pastebin.com/y3PufJ0V Thing is, though, that the hardware kept getting in the way. I discovered too slowly that the problem, as Snow said, was the hardware inherently made safe or secure computing difficult. So, my counterpoint to Dan Geer (below) pointed that out, gave many examples, and showed it must be the first step. So, we need hardware like Burroughs, System/38, SAFE (crash-safe.org), or Cambrige's CHERI that makes our job inherently easy instead of FUBAR. https://www.schneier.com/blog/archives/2014/04/dan_geer_on_hea.html#c5598568 https://www.schneier.com/blog/archives/2014/04/dan_geer_on_h... FPGA's might be modified by clever software attack along with being slow and expensive. ASIC's with right logic might be immune to software attack and fast but are EXPENSIVE. So, I was exploring S-ASIC option for non-modifiable, cheaper NRE than ASIC, and faster/cheaper than FPGA (maybe). I was going to do anti-fuse if I had to do FPGA's. Not sure what their cost or tooling is like vs typical Altera or Xilinx FPGA's. Anyway, that's what I was aiming at. Appreciate your tip. Hmm, Opterons and PowerPC G5's were done at 90nm albeit custom. Can probably squeeze quite a bit more performance out of that easic than I thought. Could always go old school and do 4-way SMP box. :)