3 ms·

eAsic is only using it's eBeam direct-write technology(which is great for prototype development for cheap) for 90nm chips. So maybe using 14nm FPGA's is better.

by minthd 11y ago

nickpsecurity 11y ago
Nextreme 1 is 90nm, Nextreme 2 is 45nm and Nextreme 3 is 28nm. Their easicopy service mentions all three. So, am I missing something? Or can't you just put a Gaisler SPARC design on an arbitrary Nextreme for S-ASIC benefits and convert it to ASIC later when cash is available? Note: Gaisler's LEON3 and LEON4 are listed in their I.P. library list for Nextreme devices. Note 2: Avoiding FPGA's except in early stage due to high unit costs and energy use. My favorite, though, are the Achronix Speedsters and their asynchronous circuits. Badass. They'll get bought out, though. (sighs)
- hga 11y ago
  Intel bought Altera; the are or were doing fab work for Achronix, which they invested in as well.
  - nickpsecurity 11y ago
    The Intel and Altera combination is especially exciting. The first time I got to see the real potential of FPGA's in practice was when SGI added them to NUMA machines. The onboard memory and interconnect meant no huge slowdown for going through PCI bottleneck. A FPGA fabric as a layer of a high-end, Intel chip with software & FPGA cooperation using on-chip interconnect would kill everything else in performance. The only thing better might be one of the POWER chips with a FPGA. Maybe IBM should buy Xilinx or Achronix... mwahahaha. I'll probably be able to afford Intel's, though, unlike IBM's. ;)
- minthd 11y ago
  While all eAsics are via programmable , only the 90nm version is programmable by eBeam. the rest requires a mask and minimum volumes - ie large expense. sorry on mobile so no link. So maybe building something on(the gaisler is a good idea) an FPGA ,and proving enough market value and finding customers (not easy) ,should be the first part , and only than , using eAsic or Fujitsu's similar service for mid-volume ?
  - nickpsecurity 11y ago
    Oh OK. I thought all of them required masks lol. I didn't know they shortcutted around that for 90nm. That's awesome! Thanks for the tip. Far as FPGA, that was my model: prove it with FPGA, get to a certain volume, and then do a S-ASIC run. Important to note that I'm focused on security-critical apps. A FGPA's reprogrammability is a risk here. I thought there was a chance I might be able to skip the FPGA off and go straight to S-ASIC if I sell customers on fixed logic being safer. The anti-fuse FPGA's are my backup plan on that although I haven't thoroughly evaluated their actual security.
    - minthd 11y ago
      The best flash FPGA that would fit your goal is probably on 65nm. if that's the case , you're better of verifying on FPGA,selling low volumes on 90nm easic -which will be far more efficient than 65 nm fpga ,expect very expensive prices at low volume , but than you could scale. BTW if security is what you sell, isn't any option to do it at the software only level and reach bulletproof security?
      - nickpsecurity 11y ago
        I used to do that with separation kernels, security through diversity, and so on. My framework (below) I eventually published for free after Snowden leaks because people weren't keeping up with attackers. http://pastebin.com/y3PufJ0V http://pastebin.com/y3PufJ0V Thing is, though, that the hardware kept getting in the way. I discovered too slowly that the problem, as Snow said, was the hardware inherently made safe or secure computing difficult. So, my counterpoint to Dan Geer (below) pointed that out, gave many examples, and showed it must be the first step. So, we need hardware like Burroughs, System/38, SAFE (crash-safe.org), or Cambrige's CHERI that makes our job inherently easy instead of FUBAR. https://www.schneier.com/blog/archives/2014/04/dan_geer_on_hea.html#c5598568 https://www.schneier.com/blog/archives/2014/04/dan_geer_on_h... FPGA's might be modified by clever software attack along with being slow and expensive. ASIC's with right logic might be immune to software attack and fast but are EXPENSIVE. So, I was exploring S-ASIC option for non-modifiable, cheaper NRE than ASIC, and faster/cheaper than FPGA (maybe). I was going to do anti-fuse if I had to do FPGA's. Not sure what their cost or tooling is like vs typical Altera or Xilinx FPGA's. Anyway, that's what I was aiming at. Appreciate your tip. Hmm, Opterons and PowerPC G5's were done at 90nm albeit custom. Can probably squeeze quite a bit more performance out of that easic than I thought. Could always go old school and do 4-way SMP box. :)

eAsic is only using it's eBeam direct-write technology(which is great for prototype development for cheap) for 90nm chips. So maybe using 14nm FPGA's is better.

by minthd 11y ago

eAsic is only using it's eBeam direct-write technology(which is great for prototype development for cheap) for 90nm chips. So maybe using 14nm FPGA's is better.

nickpsecurity 11y ago

Nextreme 1 is 90nm, Nextreme 2 is 45nm and Nextreme 3 is 28nm. Their easicopy service mentions all three. So, am I missing something? Or can't you just put a Gaisler SPARC design on an arbitrary Nextreme for S-ASIC benefits and convert it to ASIC later when cash is available? Note: Gaisler's LEON3 and LEON4 are listed in their I.P. library list for Nextreme devices. Note 2: Avoiding FPGA's except in early stage due to high unit costs and energy use. My favorite, though, are the Achronix Speedsters and their asynchronous circuits. Badass. They'll get bought out, though. (sighs)

hga 11y ago
Intel bought Altera; the are or were doing fab work for Achronix, which they invested in as well.
- nickpsecurity 11y ago
  The Intel and Altera combination is especially exciting. The first time I got to see the real potential of FPGA's in practice was when SGI added them to NUMA machines. The onboard memory and interconnect meant no huge slowdown for going through PCI bottleneck. A FPGA fabric as a layer of a high-end, Intel chip with software & FPGA cooperation using on-chip interconnect would kill everything else in performance. The only thing better might be one of the POWER chips with a FPGA. Maybe IBM should buy Xilinx or Achronix... mwahahaha. I'll probably be able to afford Intel's, though, unlike IBM's. ;)
minthd 11y ago
While all eAsics are via programmable , only the 90nm version is programmable by eBeam. the rest requires a mask and minimum volumes - ie large expense. sorry on mobile so no link. So maybe building something on(the gaisler is a good idea) an FPGA ,and proving enough market value and finding customers (not easy) ,should be the first part , and only than , using eAsic or Fujitsu's similar service for mid-volume ?
- nickpsecurity 11y ago
  Oh OK. I thought all of them required masks lol. I didn't know they shortcutted around that for 90nm. That's awesome! Thanks for the tip. Far as FPGA, that was my model: prove it with FPGA, get to a certain volume, and then do a S-ASIC run. Important to note that I'm focused on security-critical apps. A FGPA's reprogrammability is a risk here. I thought there was a chance I might be able to skip the FPGA off and go straight to S-ASIC if I sell customers on fixed logic being safer. The anti-fuse FPGA's are my backup plan on that although I haven't thoroughly evaluated their actual security.
  - minthd 11y ago
    The best flash FPGA that would fit your goal is probably on 65nm. if that's the case , you're better of verifying on FPGA,selling low volumes on 90nm easic -which will be far more efficient than 65 nm fpga ,expect very expensive prices at low volume , but than you could scale. BTW if security is what you sell, isn't any option to do it at the software only level and reach bulletproof security?
    - nickpsecurity 11y ago
      I used to do that with separation kernels, security through diversity, and so on. My framework (below) I eventually published for free after Snowden leaks because people weren't keeping up with attackers. http://pastebin.com/y3PufJ0V http://pastebin.com/y3PufJ0V Thing is, though, that the hardware kept getting in the way. I discovered too slowly that the problem, as Snow said, was the hardware inherently made safe or secure computing difficult. So, my counterpoint to Dan Geer (below) pointed that out, gave many examples, and showed it must be the first step. So, we need hardware like Burroughs, System/38, SAFE (crash-safe.org), or Cambrige's CHERI that makes our job inherently easy instead of FUBAR. https://www.schneier.com/blog/archives/2014/04/dan_geer_on_hea.html#c5598568 https://www.schneier.com/blog/archives/2014/04/dan_geer_on_h... FPGA's might be modified by clever software attack along with being slow and expensive. ASIC's with right logic might be immune to software attack and fast but are EXPENSIVE. So, I was exploring S-ASIC option for non-modifiable, cheaper NRE than ASIC, and faster/cheaper than FPGA (maybe). I was going to do anti-fuse if I had to do FPGA's. Not sure what their cost or tooling is like vs typical Altera or Xilinx FPGA's. Anyway, that's what I was aiming at. Appreciate your tip. Hmm, Opterons and PowerPC G5's were done at 90nm albeit custom. Can probably squeeze quite a bit more performance out of that easic than I thought. Could always go old school and do 4-way SMP box. :)