6 ms·

Open Source CPU Core Advances

saosebastiao 11y ago
So if these comparative benefits are objectively measurable and designs are freely available, why haven't they been commercialized yet?
- wmf 11y ago
  The spec isn't even finished and it takes time to commercialize technology.
  - hga 11y ago
    Indeed, it's way too soon to expect many, if any. MMU/protected mode draft? specs weren't released when I looked at it earlier this year (they're out, now, as I understand).
- hga 11y ago
  Echoing the other sub-thread, see this lowRISC summary from the introduction of the workshop: State of the RISC-V Nation: many companies ‘kicking the tires’. If you were thinking of designing your own RISC ISA for project, then use RISC-V. If you need a complete working support core today then pay $M for an industry core. If you need it in 6 months, then consider spending that $M on RISC-V development.
  - microcolonel 11y ago
    Given the estimates for time spent closing a deal with ARM, You could probably be actively engaged for those 6 months, and get your core in the same time frame.
    - hga 11y ago
      Is this one of the reasons MIPS is still getting design wins? How many years does it take to negotiate with ARM???
      - wtallis 11y ago
        Is MIPS still getting new design wins? I know that existing MIPS SoCs are still being used all over the place (eg. wireless routers) but is anyone actually working to put a MIPS core on a 20nm or smaller chip?
- _chris_ 11y ago
  There already are shipping, commercial RISC-V cores. The end-products are things like cameras though, so they're not very likely to make the tech blog rounds.
  - cmrx64 11y ago
    Source? Link?
    - _chris_ 11y ago
      Slide 35 from the RISC-V workshop (http://riscv.org/workshop-jun2015/riscv-intro-workshop-june2015.pdf http://riscv.org/workshop-jun2015/riscv-intro-workshop-june2...). I've also personally talked with some of the engineers who have shipped RISC-V cores in their products. The issue though is that nobody HAS to tell us they used RISC-V (that's part of the beauty of it). For small micro-controller type cores, the decision is made by some engineer to go with RISC-V instead of rolling his own ISA ($ and time are too tight to go external for a simple micro-controller), but that doesn't mean he has the power to publicly announce to the world what tools and IP his company uses in its products. Anyways, we're trying to get more people to open up so we can help make a stronger case for RISC-V by using more success stories from industry.
brachi 11y ago
The concept of 'open source hardware' is very interesting to me, however, it looks so different to software in many ways (e.g.: much harder to understand, many external dependencies to build it yourself), but maybe is just my perception due to zero knowledge of so many things.
- GauntletWizard 11y ago
  Software looks, to the layman, as very hard to understand. The infrastructure concerns of external dependencies are hard; I spent a full day configuring a build server the other day. We persevere despite these things. I doubt that the open source hardware community will ever be even a tenth the size of the software community, but if it can be large enough it can have amazing knock-on effects. Look at the outsized effect even simple things like the Raspberry Pi and Beaglebone have. They're reference boards slapped together out of commodity parts, but represent a very real gateway to software and hardware hacking to many people.
- ChuckMcM 11y ago
  I think it is just as "simple" as software, except that it is very different. Also hardware has typically been the realm of patents and software the realm of copyright when it came to protecting IP. So you can always re-implement your take on a software idea if it is only copyrighted but you can't make work alike hardware if it is patented. Fortunately a lot of hardware patents are expiring which makes the amount of useful hardware you can implement that much more useful. Over the next 5 years a huge number of microprocessor patents are due to expire into the public domain so I am looking forward to a lot of inexpensive hardware coming out of places like TSMC and China.
  - nickpsecurity 11y ago
    Not as simple at all. I can teach people how to write software pretty quick. Those same people might take years to learn to make working hardware. Without extensive tool support, it can take them a lot longer as process nodes they work on get smaller. And you don't know if it works until you shell out big money for an ASIC prototype and probably do several iterations of that. The fact that you have to spend more money to test the design is the biggest difference. Eliminate all the rest with brilliant, well studied people and you still have that huge cost on a decent process node. Services such as MOSIS help but only so much. Open-source, gate-level testing and general verification tools would be a great investment in that they reduce this significantly. Well, a full suite of open source (or cheap) EDA tools in general would be nice but that's a whole different, pessimistic discussion. :(
hga 11y ago
There's good coverage of the June workshop at http://www.lowrisc.org/ http://www.lowrisc.org/
nickpsecurity 11y ago
The RISC-V activity is very interesting. I particularly love that they did a 1.4GHz core on 48nm SOI and are working on 28nm level. This knocks out some of the early, hard work of getting competitive hardware at an advanced process node. I'd like to see two things in this work: microprogrammed variant with an assembly or HLL to microcode compiler; tagged variant like SAFE/CHERI processors with IO/MMU that seemlessly adds & removes tags during DMA. That would be way better for security-critical applications than most of what's out there. Multi-core would help, too. Meanwhile, Gaisler's SPARC cores are commercial, open-source, customizable, support up to 4 cores in Leon4, integrated with most necessary I.P., and can leverage the SPARC ecosystem. Anyone trying to do an open processor can get quite the head-start with that. A few academic and commercial works are already using it. Plus, the SPARC architecture is open as such that you only pay around $100 for the right to use its name. So, Gaisler's SPARC cores with eASIC's Nextreme seems to be the best way to rapidly get something going. The long-term bet is RISC-V and they could do well copying Gaisler's easy customization strategy. Might be doing that already with their CPU generator, etc: I just read the Rocket paper so far. The solutions built with one can include a way to transition to the other over time.
- asb 11y ago
  You might be interested in our (lowRISC's) tagged memory implementation. We describe our planned approach in http://www.lowrisc.org/docs/memo-2014-001-tagged-memory-and-minion-cores/ http://www.lowrisc.org/docs/memo-2014-001-tagged-memory-and-... My colleague Wei gave an update at the workshop a couple of weeks ago http://riscv.org/workshop-jun2015/riscv-tagged-mem-workshop-june2015.pdf http://riscv.org/workshop-jun2015/riscv-tagged-mem-workshop-...
  - ChuckMcM 11y ago
    It would be great if you also implement ECC. Memory tagging is only as good as you can trust the memory you are tagging.
    - microcolonel 11y ago
      See: rowhammer. ;-)
rwmj 11y ago
Everything to play for - 64 bit ARM is not yet established, and is a complete change from 32 bit ARM.

So if these comparative benefits are objectively measurable and designs are freely available, why haven't they been commercialized yet?

wmf 11y ago
The spec isn't even finished and it takes time to commercialize technology.
- hga 11y ago
  Indeed, it's way too soon to expect many, if any. MMU/protected mode draft? specs weren't released when I looked at it earlier this year (they're out, now, as I understand).
hga 11y ago
Echoing the other sub-thread, see this lowRISC summary from the introduction of the workshop: State of the RISC-V Nation: many companies ‘kicking the tires’. If you were thinking of designing your own RISC ISA for project, then use RISC-V. If you need a complete working support core today then pay $M for an industry core. If you need it in 6 months, then consider spending that $M on RISC-V development.
- microcolonel 11y ago
  Given the estimates for time spent closing a deal with ARM, You could probably be actively engaged for those 6 months, and get your core in the same time frame.
  - hga 11y ago
    Is this one of the reasons MIPS is still getting design wins? How many years does it take to negotiate with ARM???
    - wtallis 11y ago
      Is MIPS still getting new design wins? I know that existing MIPS SoCs are still being used all over the place (eg. wireless routers) but is anyone actually working to put a MIPS core on a 20nm or smaller chip?
_chris_ 11y ago
There already are shipping, commercial RISC-V cores. The end-products are things like cameras though, so they're not very likely to make the tech blog rounds.
- cmrx64 11y ago
  Source? Link?
  - _chris_ 11y ago
    Slide 35 from the RISC-V workshop (http://riscv.org/workshop-jun2015/riscv-intro-workshop-june2015.pdf http://riscv.org/workshop-jun2015/riscv-intro-workshop-june2...). I've also personally talked with some of the engineers who have shipped RISC-V cores in their products. The issue though is that nobody HAS to tell us they used RISC-V (that's part of the beauty of it). For small micro-controller type cores, the decision is made by some engineer to go with RISC-V instead of rolling his own ISA ($ and time are too tight to go external for a simple micro-controller), but that doesn't mean he has the power to publicly announce to the world what tools and IP his company uses in its products. Anyways, we're trying to get more people to open up so we can help make a stronger case for RISC-V by using more success stories from industry.

brachi 11y ago

The concept of 'open source hardware' is very interesting to me, however, it looks so different to software in many ways (e.g.: much harder to understand, many external dependencies to build it yourself), but maybe is just my perception due to zero knowledge of so many things.

GauntletWizard 11y ago
Software looks, to the layman, as very hard to understand. The infrastructure concerns of external dependencies are hard; I spent a full day configuring a build server the other day. We persevere despite these things. I doubt that the open source hardware community will ever be even a tenth the size of the software community, but if it can be large enough it can have amazing knock-on effects. Look at the outsized effect even simple things like the Raspberry Pi and Beaglebone have. They're reference boards slapped together out of commodity parts, but represent a very real gateway to software and hardware hacking to many people.
ChuckMcM 11y ago
I think it is just as "simple" as software, except that it is very different. Also hardware has typically been the realm of patents and software the realm of copyright when it came to protecting IP. So you can always re-implement your take on a software idea if it is only copyrighted but you can't make work alike hardware if it is patented. Fortunately a lot of hardware patents are expiring which makes the amount of useful hardware you can implement that much more useful. Over the next 5 years a huge number of microprocessor patents are due to expire into the public domain so I am looking forward to a lot of inexpensive hardware coming out of places like TSMC and China.
- nickpsecurity 11y ago
  Not as simple at all. I can teach people how to write software pretty quick. Those same people might take years to learn to make working hardware. Without extensive tool support, it can take them a lot longer as process nodes they work on get smaller. And you don't know if it works until you shell out big money for an ASIC prototype and probably do several iterations of that. The fact that you have to spend more money to test the design is the biggest difference. Eliminate all the rest with brilliant, well studied people and you still have that huge cost on a decent process node. Services such as MOSIS help but only so much. Open-source, gate-level testing and general verification tools would be a great investment in that they reduce this significantly. Well, a full suite of open source (or cheap) EDA tools in general would be nice but that's a whole different, pessimistic discussion. :(

hga 11y ago

There's good coverage of the June workshop at http://www.lowrisc.org/ http://www.lowrisc.org/

nickpsecurity 11y ago

The RISC-V activity is very interesting. I particularly love that they did a 1.4GHz core on 48nm SOI and are working on 28nm level. This knocks out some of the early, hard work of getting competitive hardware at an advanced process node. I'd like to see two things in this work: microprogrammed variant with an assembly or HLL to microcode compiler; tagged variant like SAFE/CHERI processors with IO/MMU that seemlessly adds & removes tags during DMA. That would be way better for security-critical applications than most of what's out there. Multi-core would help, too. Meanwhile, Gaisler's SPARC cores are commercial, open-source, customizable, support up to 4 cores in Leon4, integrated with most necessary I.P., and can leverage the SPARC ecosystem. Anyone trying to do an open processor can get quite the head-start with that. A few academic and commercial works are already using it. Plus, the SPARC architecture is open as such that you only pay around $100 for the right to use its name. So, Gaisler's SPARC cores with eASIC's Nextreme seems to be the best way to rapidly get something going. The long-term bet is RISC-V and they could do well copying Gaisler's easy customization strategy. Might be doing that already with their CPU generator, etc: I just read the Rocket paper so far. The solutions built with one can include a way to transition to the other over time.

asb 11y ago
You might be interested in our (lowRISC's) tagged memory implementation. We describe our planned approach in http://www.lowrisc.org/docs/memo-2014-001-tagged-memory-and-minion-cores/ http://www.lowrisc.org/docs/memo-2014-001-tagged-memory-and-... My colleague Wei gave an update at the workshop a couple of weeks ago http://riscv.org/workshop-jun2015/riscv-tagged-mem-workshop-june2015.pdf http://riscv.org/workshop-jun2015/riscv-tagged-mem-workshop-...
- ChuckMcM 11y ago
  It would be great if you also implement ECC. Memory tagging is only as good as you can trust the memory you are tagging.
  - microcolonel 11y ago
    See: rowhammer. ;-)

rwmj 11y ago

Everything to play for - 64 bit ARM is not yet established, and is a complete change from 32 bit ARM.