4 ms·
It is as of ISE-12. Some people, in fact, have reversed the datastream and can do it live, automatically, in realtime https://vjordan.info/log/fpga/full-dynamic
by Sanddancer 11y ago
It is as of ISE-12. Some people, in fact, have reversed the datastream and can do it live, automatically, in realtime https://vjordan.info/log/fpga/full-dynamic-partial-reconfiguration-sequence-on-xilinx-spartan6-lx9.html https://vjordan.info/log/fpga/full-dynamic-partial-reconfigu...
- vardump 11y agoThat looks very interesting, thanks!
- jeff_marshall 11y agoyeah, isn't that hard to get the basics by reading the docs and doing some basic experiments with explicit placement and examining the resulting bitstream. When I looked at the encryption format for the virtex 5 series it was quicker to reverse engineer it than it was to find someone within Xilinx that could explain it (just basic bit/byte order, what's covered by encryption, etc). At the end of the day, FPGA configuration logic is just another state machine ;)