3 ms·
So is it possible to load bitstream in parts, enough for basic PCIe endpoint within 100 ms to conform to PCIe spec and then load a bigger design afterwards?
by vardump 11y ago
So is it possible to load bitstream in parts, enough for basic PCIe endpoint within 100 ms to conform to PCIe spec and then load a bigger design afterwards?
- Sanddancer 11y agoYes. Xilinx chips can do on-the-fly reconfiguration. So you can have your bootstrap loader and then either load a more complete firmware from the spi chip, or over pcie
- mng2 11y agoI don't think it's supported for Spartan-6 though.
- vardump 11y agoSo it's not possible to implement compliant PCIe interface together with some bigger block with this board?
- mng2 11y agoNot with official workflows at least, and even then, you would somehow have to keep the PCIe block up during reconfiguration for compliance. I think it would be difficult to reverse engineer to that level. The easier thing to do would be to delay enumeration.
- Sanddancer 11y agoIt is as of ISE-12. Some people, in fact, have reversed the datastream and can do it live, automatically, in realtime https://vjordan.info/log/fpga/full-dynamic-partial-reconfiguration-sequence-on-xilinx-spartan6-lx9.html https://vjordan.info/log/fpga/full-dynamic-partial-reconfigu...
- vardump 11y agoThat looks very interesting, thanks!
- jeff_marshall 11y agoyeah, isn't that hard to get the basics by reading the docs and doing some basic experiments with explicit placement and examining the resulting bitstream. When I looked at the encryption format for the virtex 5 series it was quicker to reverse engineer it than it was to find someone within Xilinx that could explain it (just basic bit/byte order, what's covered by encryption, etc). At the end of the day, FPGA configuration logic is just another state machine ;)
- jeff_marshall 11y agoUgh, that time window. I once had to work with a hardware team to debug a "boot issue" where we were right on the margin due to a two-phase boot process (boot initial bitstream, check journal in flash, load active bitstream) and didn't even realize going into the debugging that we were close to the margin. It's nice to be doing plain-old software again...
- vardump 11y agoWhich platforms are the most demanding regarding PCIe time window? Which ones caused you problems?